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downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use document id: pmc-1991258, issue 7 pm5372 tse? transmission switch element datasheet proprietary and confidential released issue 7: november, 2001
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 document id: pmc-1991258, issue 7 legal information copyright ? 2001 pmc-sierra, inc. the information is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, you cannot reproduce an y part of this document, in any form, without the express written consent of pmc-sierra, inc. disclaimer none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of pm c-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. trademarks s/uni is a registered trademark of pmc-sierra, inc. spectra is a trademark of pmc-sierra, inc. spectra-2488 is a trademark of pmc-sierra, inc. tbs is a trademark of pmc-sierra, inc. tse is a trademark of pmc-sierra, inc. chess is a trademark of pmc-sierra, inc. other product and company names mentioned herein may be the trademarks of their respective owners.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 document id: pmc-1991258, issue 7 contacting pmc-sierra pmc-sierra 8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 document id: pmc-1991258, issue 7 revision history issue no. issue date details of change 7 november 2001 changed signoff page. fixed initialization procedure instruction referencing addresses 0n83h, 0n8bh, 0n93h, 0n9bh updated voltage limits on digital/lvds pins in absolute maximum ratings table. deleted ambient temperature spec. fixed 1.8v supply voltage spec. added note to lcvi that it is change from no lcv to lcv that cause lcvi. a string of lcvs will only produce 1 lcvi . consolidated power information (sequencing/filtering) to power information section. added power requirements section. removed iddop for the power supplies from the d.c characteristics table. updated thermal section. thermal section now indicates device suitable industrial applications when used with heat sink. updated lvds hot swap section. added rc filter example schematic in power filtering section updated telecombus control character table 6 august 2001 reworded dlcv description: added warning of lcv counter saturation if dlcv set high, and clarified to indicate that inverted data would have valid and invalid 8b/10b characters as result of dlcv high changed the name of the idlesel control signal echar_ovwr, and made corresponding changes to the description of the id[9:0] data bits updated thermal information in sec 18 revised power sequencing information, added max junction temp, theta ja and theta jc information, and chart of theta ja vs. airflow added sections for lvds hot swap information, power down calculations, and trace length versus fifo depth calculation changed name of etse register bit in register 0naah to eactive, hid references to tcbmode in sec 9.2 and in description of register 0nb0h the device id field is now ?0001 instead of ?0000? in register 0010h. the jtag version number has been changed to 1h in table 16. the j0mask bit has been added to registers 0n80h, 0n88h, 0n90h, 0n98h to support applications which require floating input links to remain activated. added the ij0rordr bit to register 0na2. added the ej0r0rdr bit to register onaa. 5 march 2001 added warning of lcv counter saturation if dlcv set high.in register descriptions changed the name of the idlesel control signal to character overwrite, and made corresponding changes to the description of the id[9:0] data bits
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 document id: pmc-1991258, issue 7 issue no. issue date details of change updated reliability information (sec 23), and thermal information in sec 18. revised power sequencing information, added max junction temp, theta ja and theta jc information, and chart of theta ja vs. airflow added sections for lvds hot swap information, power down calculations, and trace length versus fifo depth calculation . changed name of etse register bit in register 0naah to eactive, removed references to tcbmode in sec 9.2 and in description of register 0nb0h revised sec 9.2 and 9.2.1 to further de-document telecombus mode. changed vil(max) to 0.8v and vt+ to 2.2v based on characterization report. revised theta ja vs. airflow table and theta jc value with 560ubga information. updated operating power to 9.86w. changed operating temperature range to t c = -40c to tj=120c. revised section on j0 synchronization. 4 october 2000 added instructions to check csu lock status and to center transmit fifos in section 12.5. added section 12.8. added diagnostic note in tj0fp pad description, amended tdi pad description to indicate there is no pull up resistor on the pad, removed part of res/resk pad description from datasheet, removed atmsb, and dtmsb register bits from datasheet, redocumented clear behavior of indication register bits when wcimode=1, amended legal range of values for rj0dly: 1 to 9719, added explanatory text to busy register bits, removed rxlbsel from datasheet, added functional timing diagram for page switching using spsel, ipsel, and epsel register bits, corrected tj0dly description to indicate that the time to tj0fp is tj0dly+2, amended dlcv register bit description, amended center register bit description, to indicate that fifo depth is 3-4 deep following centering operation, removed rdc mode from j0ins register bit description, corrected boundary scan register table: previously reverse ordered, and oeb_d(i) incorrectly identified as io_cell, updated system ?j0? timing diagram, added input pad tolerance, output pad overshoot, latchup current for resk in absolute maximum ratings table, added typical and max operating currents to d.c characteristics table, corrected mechanical information table with respect to package thickness. 3 april 2000 finalized pin out, register setting and functions 2 january 2000 register description modification, package and pinout information, added functional timing descriptions and scan test registers, changed tolerances of 1.8v supply to +-5%. 1 june 1999 document created
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 document id: pmc-1991258, issue 7
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 document id: pmc-1991258, issue 7 table of contents legal inform ation .............................................................................................................. .. 2 copyright............................................................................................................. 2 disclaimer ........................................................................................................... 2 trademarks ......................................................................................................... 2 contacting pmc-sierra ....................................................................................................... 3 revision history ............................................................................................................... ... 4 table of contents .............................................................................................................. .. 7 list of figures................................................................................................................ .... 10 list of tables ................................................................................................................. .... 11 list of registers .............................................................................................................. .. 13 1 features .................................................................................................................... 15 2 applicat ions ............................................................................................................... 16 3 references ................................................................................................................ 17 4 application examples ................................................................................................ 18 4.1 motivating ap plications ..................................................................................... 18 4.2 tse fabric scaling ........................................................................................... 19 4.3 redundant fabrics ........................................................................................... 23 4.4 non-sts-48 loads ........................................................................................... 23 4.5 tse fabric packaging ...................................................................................... 23 5 block diagram ........................................................................................................... 24 6 description ................................................................................................................ 25 7 pin diagram............................................................................................................... 27 8 pin descrip tion .......................................................................................................... 31 9 functional description............................................................................................... 45 9.1 lvds overview................................................................................................. 45 9.1.1 lvds receiver (rxlv)........................................................................... 46 9.1.2 lvds transmitter (txlv) ....................................................................... 46 9.1.3 lvds transmit reference (txref)....................................................... 47 9.1.4 data recovery unit (dru) ..................................................................... 47 9.1.5 parallel to serial converter (piso) ........................................................ 48
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 document id: pmc-1991258, issue 7 9.1.6 clock synthesis unit (csu) ................................................................... 48 9.2 receive 8b/10b frame aligner (r8fa) ............................................................ 48 9.2.1 character alignment ............................................................................... 49 9.2.2 frame alignment .................................................................................... 50 9.2.3 fifo buffer ............................................................................................. 51 9.2.4 frame counter ....................................................................................... 51 9.3 ingress time switch element (itse)................................................................ 51 9.4 space switch stage (sswt) ............................................................................ 51 9.5 egress time switch element (etse) ............................................................... 52 9.6 transmit 8b/10b disparity encoder (t8de) ..................................................... 52 9.7 clock synthesis and transmit reference digital wrapper (cstr) ................. 53 9.8 fabric latency .................................................................................................. 53 9.9 jtag support ................................................................................................... 53 9.10 microprocessor interface .................................................................................. 54 10 normal mode register description ........................................................................... 59 11 test features description ....................................................................................... 121 11.1 jtag test port................................................................................................ 122 11.1.1 boundary scan cells ............................................................................ 123 12 operation................................................................................................................. 126 12.1 power conservation ....................................................................................... 126 12.2 lvds optimizations........................................................................................ 127 12.3 lvds hot swapping ....................................................................................... 128 12.4 lvds trace lengths....................................................................................... 128 12.5 jtag support ................................................................................................. 129 12.5.1 tap controller ...................................................................................... 131 12.5.2 states.................................................................................................... 133 12.5.3 instructions ........................................................................................... 134 12.6 initialization procedure ................................................................................... 135 12.7 interrupt service routine ................................................................................ 136 12.8 interpreting the status of receive decoders .................................................. 136 12.9 accessing indirect registers .......................................................................... 137 12.10 using the performance monitoring features.................................................. 137
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 document id: pmc-1991258, issue 7 12.11 ?j0? synchronization of the tse in a chess system ................................ 138 12.12 synchronized control setting changes.......................................................... 142 12.13 fabric rules of composit ion. ......................................................................... 142 12.13.1 interconnections ............................................................................. 142 12.13.2 behavioural descripti ons of components ...................................... 142 12.13.3 rules of com position ..................................................................... 143 12.13.4 examples of legal composition..................................................... 144 13 functional timing .................................................................................................... 148 13.1 receive interface timing ................................................................................ 148 13.2 transmit interface timing ............................................................................... 149 14 absolute maximum ratings .................................................................................... 151 15 power information ................................................................................................... 152 15.1 power requirements ...................................................................................... 152 15.2 power sequencing.......................................................................................... 153 15.3 power supply filtering.................................................................................... 153 16 d.c. characteristics ................................................................................................ 155 17 microprocessor interface timing characteristics .................................................... 157 18 a.c. timing characteristics ..................................................................................... 161 18.1 input timing .................................................................................................... 161 18.2 output timing ................................................................................................. 162 18.3 reset timing................................................................................................... 163 18.4 serial telecombus interface ........................................................................... 164 18.5 jtag port interface ........................................................................................ 164 19 ordering information ............................................................................................... 166 20 thermal information ................................................................................................ 167 21 mechanical information ........................................................................................... 169
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 document id: pmc-1991258, issue 7 list of figures figure 1 representative tse applic ation ......................................................................... 18 figure 2 fabric with one plane of depth one. ................................................................. 19 figure 3 fabric with two planes of depth one. ............................................................... 20 figure 4 fabric with four planes of depth one. .............................................................. 20 figure 5 fabric with one plane of depth three and height thirty-two........................... 21 figure 6 fabric with one plane of depth three and height sixty-four ........................... 22 figure 7 generic lvds link block diagram..................................................................... 45 figure 8 input observation cell (in_cell) .................................................................... 124 figure 9 output cell (out_cell) .................................................................................. 124 figure 10 bidirectional cell (io_cell)........................................................................... 125 figure 11 layout of output enab le and bidirect ional ce lls ............................................ 125 figure 12 boundary scan architecture ........................................................................... 130 figure 13 tap controller finite state machine .............................................................. 132 figure 14 ?j0? synchronization control .......................................................................... 141 figure 15 fabric components ........................................................................................ 143 figure 16 load:load null fabrics. .............................................................................. 144 figure 17 tbs fabri cs (non-redundant). ........................................................................ 145 figure 18 tse fabric (redundant). ................................................................................. 146 figure 19 tse fabric with differing path lengths.......................................................... 147 figure 20 receive interface timing ................................................................................ 148 figure 21 transmit interface timing ............................................................................... 149 figure 22 cmp timing .................................................................................................... 150 figure 23 psel timing ................................................................................................... 150 figure 24 sample rc filter ............................................................................................ 154 figure 25 microprocessor interface read timing........................................................... 158 figure 26 microprocessor interface write timing........................................................... 159 figure 27 tse input timing ............................................................................................ 161 figure 28 tse output timing ......................................................................................... 162 figure 29 rstb timing................................................................................................... 163 figure 30 jtag port interface timing ............................................................................ 165
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 document id: pmc-1991258, issue 7 list of tables table 1 pin description lv ds ports (256 signals).......................................................... 31 table 2 pin description tse cont rol and clocking (5 signals) ........................................ 36 table 3 pin description microprocessor interface (34 signals)........................................ 36 table 4 pin description jt ag port (5 signals)................................................................. 38 table 5 pin description exter nal resistors (8 signals) .................................................... 38 table 6 pin description analog test bus (8 signals) ....................................................... 38 table 7 pin description digita l i/o power (36 signals) .................................................... 40 table 8 pin description analog low voltage power (28 signals)..................................... 41 table 9 pin description analog power ............................................................................. 41 table 10 pin description ground (76 signals) .................................................................. 42 table 11 pin description no connect (20 signals) ........................................................... 43 table 12 telecombus control characters........................................................................ 48 table 13 control word index ............................................................................................ 86 table 14 instruction register (length ? 3 bits) ............................................................... 122 table 15 identifica tion register ...................................................................................... 122 table 16 boundary scan regi ster length ? 57 bits ....................................................... 122 table 17 power reduction for disabled links ................................................................ 126 table 18 absolute maximum ratings ............................................................................. 151 table 19 power requirements ....................................................................................... 152 table 20 d.c. characteristics ......................................................................................... 155 table 21 microprocessor in terface read access ........................................................... 157 table 22 microprocessor interface write access ........................................................... 159 table 23 tse input timing (figure 27)........................................................................... 161 table 24 tse output timing (figure 28)........................................................................ 162 table 25 rstb timing (figure 29) ................................................................................. 163 table 26 serial telecombus interface............................................................................ 164 table 27 jtag port interface (figure 30)....................................................................... 164 table 28 outside plant thermal information ................................................................ 167 table 29 device compact model 3 ................................................................................. 167 table 30 heat si nk requirements ................................................................................ 167
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 document id: pmc-1991258, issue 7
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 document id: pmc-1991258, issue 7 list of registers register 0000h: tse master reset, identity ................................................................... 60 register 0001h: tse master clock activity and accu mulation trigger .......................... 61 register 0002h: tse ma ster configuration..................................................................... 63 register 0003h: tse master interrupt block identifie r.................................................... 65 register 0004h: tse master r8fa interrupt source #1................................................. 67 register: 0005h: tse master r8fa interrupt source #2................................................ 68 register 0006h: tse master r8fa interrupt source #3................................................. 69 register 0007h: tse master r8fa interrupt source #4................................................. 70 register 0008h: tse master t8de interrupt source #1................................................. 71 register 0009h: tse master t8de interrupt source #2................................................. 72 register 000ah: tse master t8de interrupt source #3 ................................................ 73 register 000bh: tse master t8de interrupt source #4 ................................................ 74 register 000ch: tse mast er itse interrupt source ...................................................... 75 register 000dh: tse master etse interrupt source ..................................................... 76 register 000eh: tse master cstr interrupt source..................................................... 77 register 000fh: tse ma ster user defined..................................................................... 78 register 0010h: tse ma ster jtag id high.................................................................... 79 register 0011h: tse master jtag id low..................................................................... 80 register 0020h, 00024h, 0028h, 002ch: cstr #1 ? #4 control................................... 81 register 0021h, 00025h, 0029h, 002dh: cstr #1 ? #4 interrupt enable and csu lock status ............................................................................................ 82 register 0022h, 00026h, 002ah, 002eh: cstr #1 ? #4 interrupt indication ................ 83 register 0040h: sswt rj0fp delay .............................................................................. 84 register 0041h: sswt indirect control address ............................................................. 85 register 0042h: sswt indirect control data................................................................... 88 register 0043h: sswt interrupt enable .......................................................................... 90 register 0044h: sswt interrupt status ........................................................................... 91 register 0047h: sswt tj0fp delay............................................................................... 92 register 0n80h, 0n88h, 0n90h, 0n98h: port set #1 - #16 r8fa #1 - #4 control and status....................................................................................................... 93
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 document id: pmc-1991258, issue 7 register 0n81h, 0n89h, 0n91h, 0n99h: port set #1 - #16 r8fa #1 - #4 interrupt status ............................................................................................... 96 register 0n82h, 0n8ah, 0n92h, 0n9ah: port set #1 - #16 r8fa #1 - #4 line code violation count...................................................................................... 98 register 0n83h, 0n8bh, 0n93h, 0n9bh: port set #1 - #16 rxlv and dru #1 - #4 control ....................................................................................................... 99 register 0na0h: port set #1 - #16, itse indirect address............................................ 101 register 0na1h: port set #1 - #16 itse indirect data .................................................. 103 register 0na2h: port set #1 - #16 itse configuration ................................................. 105 register 0na3h: port set #1 - #16, itse interrupt status ............................................. 107 register 0na8h: port set #1 - #16, etse indirect address .......................................... 108 register 0na9h: port set #1 - #16, etse indirect data................................................ 110 register 0naah: port set #1 - #16, etse configuration .............................................. 112 register 0nabh: port set #1 - #16, etse interrupt status ........................................... 114 register 0nb0h, 0nb8h, 0nc0h, 0nc8h: port set #1 - #16, t8de #1 - #4 control and status ........................................................................................ 115 register 0nb1h, 0nb9h, 0nc1h, 0nc9h: port set #1 - # 16 t8de #1 - #4 interrupt status ............................................................................................. 117 register 0nb4h, 0nbch, 0nc4h, 0ncch: port set #1 - #16 t8de #1 - #4 test pattern .......................................................................................................... 118 register 0nb5h, 0nbdh, 0nc5h, 0ncdh: port set #1 - #16, txlv and piso control .......................................................................................................... 119
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 document id: pmc-1991258, issue 7 1 features implements a time-space-time fabric with sts-1/au-3 granularity provides 64 ingress sts-12 links for a total of 64*12 = 768 sts-1 streams provides 64 egress sts-12 links consisting of 768 sts-1 streams supports non-blocking permutation switchin g of 768 sts-1 flows at sts-1 granularity interfaces to sts-48 and sts-192 devices by aggregating 4 and 16 sts-12 flows respectively supports multicast and broadcast of sts-1 streams supports multi-plane (inverse multiplexed) switch architectures in conjunction with the pm5310 tbs? device and pm7390 s/uni?-mach48 recovers clock and data at each ingress port, synchronizes with an internal 77.76 mhz clock, and produces egress streams with a common 777.6 mhz clock detects and reports inactive or errored lvds links via the microprocessor interface supports two sets of switch settings and a controlled method of changing settings on sts-1 frame boundaries supports multiple fabric architectures that range from 40 gb/s (one device) to 160 gb/s (four devices) in a single stage, and up to 2.5 tb/s using multi-stage fabrics ingress to egress sts-1 switching latency of approximately 840ns supported by an efficient algorithm to compute control settings for all permutation loads for all supported fabric architectures. algorithms are also available for multicast/broadcast allocation 1.8v cmos core and 3.3v cmos/lvds input/output requires no external rams or logic parts provides a standard ieee 1149.1 jtag port power consumption of 8.3 w (typical) packaged in a 560 pin 40mm by 40mm ultrabga supports a 16-bit microprocessor interface that is used to initialize the device, to write switch settings into on-chip control tables, and to monitor device performance
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 document id: pmc-1991258, issue 7 2 applications optical cross connects sts-1 cross connects multi-service provisioning platforms sonet/sdh add/drop multiplexers sonet/sdh digital cross connects
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 document id: pmc-1991258, issue 7 3 references 1. ansi ? t1.105-1995, ?synchronous optical network (sonet) ? basic description including multiplex structure, rates, and formats?, 1995 2. bell communications research ? sonet tran sport systems: common generic criteria, gr-253-core, issue 2, revision 2, january 1999 3. itu, recommendation g.707 ? ?digital tran smission systems ? terminal equipments ? general?, march 1996 4. ieee 802.3, ?carrier sense multiple access with collision detection (csma/cd) access method and physical layer specifications?, section 36.2, 1998 5. a.x. widmer and p.a. franaszek, ?a dc-bal anced, partitioned-block, 8b/10b transmission code,? ibm journal of research and development, vol. 27, no 5, september 1983, pp 440- 451 6. u.s. patent no. 4,486,739, p.a. franaszek and a.x. widmer, ?byte oriented dc balanced (0,4) 8b/10b partitioned block tr ansmission code,? december 4, 1984 7. ieee std 1596.3-1996, ?ieee standard for low-voltage differential signals (lvds) for scalable coherent interface (sci)?, approved march 21, 1996 8. l.r. ford, d.r. fulkerson, ?flows in ne tworks??, maximum cardinality matchings in bipartite graphs
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 document id: pmc-1991258, issue 7 4 application examples 4.1 motivating applications the pm5372 device is principally used in app lications where cross-connecting of sts-1/au-3 streams is required. such applications incl ude add-drop multiplexers, sts-1 cross-connects, optical cross-connects and multi-service provisioning platforms. multi-service provisioning platforms may also use an sts-1 cross-connect fabric to decouple the physical layer from the service layer. these products may integrate the dcs, adm, switching, routing and broadcast capabilities. part of an example architecture is illustrated in figure 1. in this application, the cross-connect fabric consists of the tse? devices. the tse devices support a time-space-time switch architecture. note that the following ex ample has two complete tse fabrics to support ?1+1? fabric redundancy. the tses labeled fab a compose the primary or working fabric. the tses labeled fab b compose the secondary or protect fabric. figure 1 representative tse application optics spectra- 2488 tbs(0) fab a tse(0) fab a tse(3) fab b tse(0) fab b tse(3) optics spectra- 2488 tbs(1) optics spectra- 2488 tbs (31) s/uni- mach48 s/uni- mach48 s/uni- mach48 sonet ring / phy layer dual tse fabrics multi-service layer ... ... ... ... ... ...
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 document id: pmc-1991258, issue 7 4.2 tse fabric scaling independent of the application described above, the tse is a general sts-1/au-3 granularity fabric. as a fabric, it supports multiple architectures which scale in aggregate bandwidth from 40 gb/s to 2.5 tb/s (and larger, until limited by packaging concerns). fabrics up to 160 gb/s (i.e. 4 tse devices) are supported in a single stage architecture. all fabrics are rearrangably non- blocking under all 100% loaded permutations of unicast traffic. scaling of these tse architectures is accomplished by two mechanisms: division of the fabric into multiple planes , and deepening of the fabric into multiple stages , where each stage may be of some power-of-two height , up to a maximum depending on the number of stages . a plane of tses within a fabric is defined as a group of connected tses unconnected to other tse groups in the fabric. a multiple plane fabric requires distributing the connections of each serializer?s i/o to all planes. the pm5310 tbs device with its four serial streams, can be used to implement a one, two, or four plane fabric. figure 2 illustrates the simplest tse fabric. one tse is connected to 16 full-duplex sts-48 loads via 16 tbs devices, providing an aggregate switch bandwidth of 40 gb/s using one tse and 16 tbs devices. the tbs devices in figure 2 are used only to serialize parallel telecombuses (p-tcb). where oc-48 load devices have serial telecombuses (s-tcb) interfaces, the tbs devices are unnecessary. each sts-48 load is connected by four full-duplex links. the links from the loads to the tbs devices are parallel telecombuses (p-tcb), which are 4 * 8 bits at 77.76 mhz; all links to/from tse devices are serial telecombuses (s-tcb), which are 4 * 777.6 mhz lvds links. in each depth one tse fabric, the tse devices form non- blocking time-space-time fabrics. figure 2 fabric with one plane of depth one. tbs (0) tse tbs (15) ... 4 4 4 4 sts-48 (0) sts-48 (15) (sts-48 sources = 16; aggregate bandwidth = 40 gb/s; tse chip count = 1; tbs chip count = 16) figure 3 illustrates a two-plane tse fabric. each of 32 full-duplex sts-48 loads on 32 tbs devices are connected by two lvds links each to each of two tse devices. the aggregate switch bandwidth is 80 gb/s at a cost of two tse devices and 32 tbs devices.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 document id: pmc-1991258, issue 7 figure 3 fabric with two planes of depth one. tbs (0) tse tbs (31) 4 4 2 2 sts-48 (0) sts-48 (31) tse 2 2 ... ... (sts-48 sources = 32; aggregate bandwidth = 80 gb/s; tse chip count = 2; tbs chip count = 32) in multi-plane tse fabrics, tbs devices (or load devices with equivalent s-tcb ports) perform the load balancing required by the invers e-multiplexed (i.e., multi-plane) tse fabric. figure 4 illustrates a four-plane tse fabric, representing the largest sts-48 fabric with a depth of one. each of 64 full-duplex sts-48 loads on 64 tbs devices are connected by one lvds link each to each of four tse devices. the aggregate switch bandwidth is 160 gb/s at a cost of four tse devices and 64 tbs devices. figure 4 fabric with four planes of depth one. tbs (0) tse tbs (63) ... 4 4 1 1 sts-48 (0) sts-48 (63) tse 1 1 ... tse tse 1 1 1 1 .
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 document id: pmc-1991258, issue 7 (sts-48 sources = 64; aggregate bandwidth = 1 60 gb/s; tse chip count = 4; tbs chip count = 64) figure 5 illustrates a three stage tse fabric ( depth = 3), with a height of 32. each of 512 full- duplex sts-48 loads on 512 tbs devices are connected by four lvds links each to a tse. the receive ports for each tse in column 0 is connected to the 4 transmit lvds links of 16 tbs devices, for example tse(0,0) receives from tbs(0) through tbs(15). the transmit lvds links of each tse in column 0 fan out to all 32 tses in column 1, with 2 links per transmit/receive device pair. transmit links for column 1 tses fan out similarly to column 2 tses. transmit links of column 2 tses connect back to the tbs devices. each column 2 tse connects with 16 tbs devices, with 4 transmit lvds links per device pair, for example tse(0,2) transmits to tbs(0) through tbs(15).the aggregate switch bandwidth is 1,280 gb/s using 96 tse devices and 512 tbs devices. figure 5 fabric with one plane of depth three and height thirty-two. tbs (0) tse (0,0) tse (0,1) tse (0,2) 2 2 4 4 fabric row 0: tbs (511) sts-48 (511) tse (31,0) 4 tse (31,1) tse (31,2) 4 4 4 fabric row 31 ... ... ... ... ... sts-48 (0) 4 2 2 tbs (15) sts-48 (15) 4 ... ... tbs (496) sts-48 (496) 4 ... ... column 0 column 1 column 2 4 (sts-48 sources = 512; aggreg ate bandwidth 1280 gb/s; tse chip count = 96; tbs chip count = 512)
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 document id: pmc-1991258, issue 7 fabrics with depth greater than one have redundant internal time stages where tse devices communicate with tse devices. these redundant stages can be set to the identity mapping at startup, and then ignored during system operation. figure 6 illustrates the largest single-plane, three-stage fabric that has an aggregate bandwidth of 2560 gb/s. the difference between this example and the one shown in figure 5 is that this one extends the fabric to its full height of 64 tse devices, whereas the fabric in figure 5 limited the height to 32 tse devices. figure 6 fabric with one plane of depth three and height sixty-four tbs (0) tse (0,0) tbs (1023) sts-48 (0) sts-48 (1023) tse (63,0) 4 . tse (0,1) tse (63,1) tse (0,2) tse (63,2) 4 4 4 4 4 1 11 1 1 11 4 4 fabric row 0: fabric row 63: 1 ... ... ... ... ... (sts-48 sources = 1024; aggregate bandwidth = 2560 gb/s; tse chip count = 192; tbs chip count = 1024) larger tse fabrics can be constructed in several ways by extending the architectural techniques shown above. in particular, the fabric shown in figure 6 can be sliced into two or four planes (for sts-48), yielding fabrics up to 5120 gb/s or 10,240 gb/s, respectively. furthermore, five stages of tse devices can be used to build deeper fabrics (which permit greater height ). additionally, sts-192 fabrics with up to 16 planes of tse devices can be constructed.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 document id: pmc-1991258, issue 7 4.3 redundant fabrics all of the tse fabrics discussed above can be repl icated to form dual redundant fabrics (as shown in figure 1) for 1+1 equipment protection. support for this feature is independent of the tse - it requires error detection and dual ports in the feeder devices (e.g. tbs and the s/uni- mach48) as well as dual lvds ports and failure switch-over logic in the tbs. 4.4 non-sts-48 loads the tse also supports both sts-12 and sts-192 loads. each sts-12 device consumes only one parallel port (8 bits at 77.76 mhz) on a tbs or s/uni-mach48, whereas an sts-48 device consumes all four parallel ports (4 * 8 bits at 77.76 mhz) on a tbs or s/uni-mach48. each sts-192 device consumes all four parallel ports on four tbs or s/uni-mach48 devices. the tse/tbs (or s/uni-mach48) fabric sees only se ts of sts-12 ports; as the tse/tbs (s/uni- mach48) fabric supports any sts-1 to sts-1 perm utation, the possible collection of sts-1s or sts-12s into sts-48s or sts-192s is immaterial to the fabric. sts-192 loads permit tse fabrics to grow to eight or sixteen planes, in which two or one sts-12 lvds links are used to communicate between the sts-192 sources and the multiple planes of the fabric. in such fabrics, tse devices can be used to gather/scatter traffic from lower aggregate rate devices into the multi-plane fabric (it is necessary that all such lower rate devices be able to communicate with all planes of any fabric). where sts-12 loads are used in multi-plane fabrics, the tbs is used to distribute and gather traffic across the multiple planes of the fabric. it is also possible to use an additional tse to perform this sts-12 grooming function for up to 32 sts-12 sources. 4.5 tse fabric packaging tse fabrics can be packaged on pcbs in a variety of ways. the 777.6 mhz lvds serial links are used to communicate between the port cards and the fabric cards. with careful pcb, connector, and back-plane design, no bus drivers will be required. in such packaging of tse fabrics, the concentration of all the tse devices onto special fabric cards, and the non-involvement of the tbs devices in the switching function (they only serialize the telecombus and provide the fan-out to (possible) dual fabrics) permit all automatic protection switching (aps) switch setting changes to be concentrated on the fabric cards; general connection establishment setup requires access to the connected tbs devices.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 document id: pmc-1991258, issue 7 5 block diagram block diagram 0 cross-bar space switch element sswt rn[1] rp[1] tn[1] tp[1] microprocessor interface jtag trstb tck tms tdi tdo d[15:0] a[12:0] csb ale rdb wrb rstb intb lvds transmit reference txref clock synthesizer csu cstr sysclk ingress time switch element itse #1 lvds receiver rxlv #1 data recovery unit dru #1 rx 8b/10b frame aligner r8fa#1 rn[2] rp[2] lvds receiver rxlv #2 data recovery unit dru #2 rx 8b/10b frame aligner r8fa#2 rn[3] rp[3] lvds receiver rxlv #3 data recovery unit dru #3 rx 8b/10b frame aligner r8fa#3 rn[4] rp[4] lvds receiver rxlv #4 data recovery unit dru #4 rx 8b/10b frame aligner r8fa#4 rn[61] rp[61] ingress time switch element itse #16 lvds receiver rxlv #61 data recovery unit dru #61 rx 8b/10b frame aligner r8fa#61 rn[62] rp[62] lvds receiver rxlv #62 data recovery unit dru #62 rx 8b/10b frame aligner r8fa#62 rn[63] rp[63] lvds receiver rxlv #63 data recovery unit dru #63 rx 8b/10b frame aligner r8fa#63 rn[64] rp[64] lvds receiver rxlv #64 data recovery unit dru #64 rx 8b/10b frame aligner r8fa#64 egress time switch element etse #1 lvds transmitter txlv #1 serializer piso #1 tx 8b/10b disp. encoder t8de#1 tn[2] tp[2] lvds transmitter txlv #2 serializer piso #2 tx 8b/10b disp. encoder t8de#2 tn[3] tp[3] lvds transmitter txlv #3 serializer piso #3 tx 8b/10b disp. encoder t8de#3 tn[4] tp[4] lvds transmitter txlv #4 serializer piso #4 tx 8b/10b disp. encoder t8de#4 tn[61] tp[61] egress time switch element etse #16 lvds transmitter txlv #61 serializer piso #61 tx 8b/10b disp. encoder t8de#61 tn[62] tp[62] lvds transmitter txlv #62 serializer piso #62 tx 8b/10b disp. encoder t8de#62 tn[63] tp[63] lvds transmitter txlv #63 serializer piso #63 tx 8b/10b disp. encoder t8de#63 tn[64] tp[64] lvds transmitter txlv #64 serializer piso #64 tx 8b/10b disp. encoder t8de#64 cmp tj0fp rj0fp
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 document id: pmc-1991258, issue 7 6 description the pm5372 tse is a monolithic cmos integrated circuit that performs sts-1 granularity cross-connecting. the tse receives data on 64 777.6 mhz lvds links. each link contains a sts-12/stm-4 stream. bytes on the links are carried as 8b/10b characters. at minimum, each stream must include a 8b/10b special framing character to allow the tse to character and frame align the stream. additionally, the tse can support a serial telecombus protocol, in which telecombus control signals are encoded as 8b/10b special ch aracters. data is switched through the tse in 8b/10b code words. the tse performs character and frame alignment on each stream. the tse aligns data from multiple sources prior to switching the data. data alignment is achieved by synchronizing the frame aligners in transmitting their aligned frame data. the tse switches the sts-12 aligned data streams at sts-1 granularity through time, space, and then time switch stages. the time switch stages perform timeslot interchange on the sts-12 data stream. the space switch stage switches data from one sts-12 pipe to another. each time slot is switched independently in the space switch stage. the tse supports software configurable dual-page switch settings. this permits new switch settings to be stored in the inactive page of control settings, while the tse operates on the active page of control settings. the tse switches between control setting pages on sts-1 frame boundaries for hitless switchover through the device page select pin cmp. block-by-block switchover is facilitated by software configurable page select bits. the tse transmits data on 64 777.6 mhz lvds links. as on the receive side, a link contains a sts-12/stm-4 stream, encoded as 8b/10b characters. prior to transmission and following switching, the tse must reprocess each st ream for correct 8b/10b disparity. the function of the tse is explained with respect to the block diagram. the flow in the block diagram is left-to-right. the left-most three units on each of the 64 sts-12 flows (lvds receiver, data recovery unit, and receive 8b/10b frame aligner) receive, decode and align the incoming flows. the ingress time switch elem ents perform timeslot interchange on the sts-12 stream. the space switch element permits arbitrary permutations over space during each time step. the egress time switch elements implements another sts-12 timeslot interchange. the right-most three units (transmit 8b/10b disparity encoder, serializer, and lvds transmitter) re- encode, serialize and transmit the output streams. switch control is distributed among the time and space switching modules. switch control is organized into pages of control words which determine what permutations are implemented for each of the twelve sts-1 positions (in time) at each of the 64 ports (in space) for the switching stage. the microprocessor interface is used to initialize the tse and to access the switch control settings. jtag is supported on non-lvds signal for board testing. the three modules (cstr, csu, and txref) provide clock and voltage references for the other lvds modules.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 document id: pmc-1991258, issue 7 multiple fabric architectures can be supported, although the focus is on fabrics which are non- blocking under 100% permutation loads. the tse also supports multicast capabilities.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 document id: pmc-1991258, issue 7 7 pin diagram the tse is packaged in a cust om ultra-bga with 560 balls. pin diagram top left corner 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a vss vss vss vss a[4] a[7] a[10] vddi vss tp[50] vss tp[52] vss rn[51] vss tp[53] vss tp[56] vss b vss vddo vddo vddo a[5] a[8] a[11] nc tp[49] tn[50] nc tn[52] rn[50] rp[51] rn[52] tn[53] tp[55] tn[56] avdl c vss vddo vddo vddo a[6] vddi vddi nc tn[49] tp[51] vddi rn[49] rp[50] avdl rp[52] tp[54] tn[55] rn[53] vddi d vss vddo vddo vddo vddi a[9] vddi atb0[4] atb1[4] tn[51] avdh rp[49] vddi vddi avdh tn[54] vddi rp[53] avdh e a[3] a[2] a[0] a[1] f vss vddi nc avdh g resk res rn[48] rp[48] h vss rn[47] rp[47] avdl j rn[46] rp[46] rn[45] rp[45] k vss tp[48] tn[48] avdh l tp[47] tn[47] tp[46] tn[46] m vss tp[45] tn[45] vddi n rn[44] rp[44] rn[43] rp[43] p vss rn[42] rp[42] avdh r vddi avdl rn[41] rp[41] t vss tp[44] tn[44] vddi u tp[43] tn[43] tp[42] tn[42] v tp[41] tn[41] csu _ avdl csu _ avdl w rn[40] rp[40] csu _ avdl csu _ avdh y rn[38] rp[38] rn[39] rp[39]
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 document id: pmc-1991258, issue 7 pin diagram top right corner 2019181716151413121110987654321 rn[54] rn[56] tp[57] tp[59] vss vddi vss rn[60] vss tp[63] vss rn[62] vss resk vss a[12]/tr s vss vss vss vss a rp[54] rp[56] tn[57] tn[59] tp[60] avdl rn[58] rp[60] tp[61] tn[63] tp[64] rp[62] rn[63] res nc sysclk vddo vddo vddo vss b rn[55] csu _ avdl csu _ avdl tp[58] tn[60] rn[57] rp[58] rn[59] tn[61] tp[62] tn[64] rn[61] rp[63] rn[64] nc rj0fp vddo vddo vddo vss c rp[55] csu _ avdh csu _ avdl tn[58] vddi rp[57] avdh rp[59] vddi tn[62] avdh rp[61] avdl rp[64] avdh vddi vddo vddo vddo vss d cmp csb tdo vddi e wrb ale rdb vddi f vddi vddi tj0fp intb g atb0[1] nc nc vddi h atb1[1] tn[1] tp[1] vss j tn[3] tp[3] tn[2] tp[2] k avdh vddi nc vss l rp[1] rn[1] tn[4] tp[4] m vddi rp[2] rn[2] vss n vddi avdl rp[3] rn[3] p avdh rp[4] rn[4] vss r tn[6] tp[6] tn[5] tp[5] t vddi tn[7] tp[7] vss u rp[5] rn[5] tn[8] tp[8] v avdh vddi avdl vss w rp[7] rn[7] rp[6] rn[6] y
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 document id: pmc-1991258, issue 7 pin diagram bottom left corner a a vss avdl vddi avdh a b tp[40] tn[40] rn[37] rp[37] a c vss tp[39] tn[39] vddi a d tp[37] tn[37] tp[38] tn[38] a e vss rn[36] rp[36] avdh a f rn[35] rp[35] avdl vddi a g vss rn[34] rp[34] vddi a h tp[36] tn[36] rn[33] rp[33] aj vss nc vddi avdh a k tp[34] tn[34] tp[35] tn[35] a l vss tp[33] tn[33] atb1[3] a m vddi nc nc atb0[3] a n d[14] vddi vddi d[15] a p vddi d[11] d[13] d[12] ar vddi d[8] d[10] d[9] a t vss vddo vddo vddo vddi avdh rp[32] avdl rp[29] avdh tn[30] vddi rp[27] avdh rp[25] vddi tn[26] csu_avd l csu_av dh a u vss vddo vddo vddo rstb nc rn[32] rp[31] rn[29] tn[32] tp[30] tn[29] rn[27] rp[26] rn[25] tn[28] tp[26] csu_avd l csu_avd l a v vss vddo vddo vddo trstb nc res rn[31] rp[30] tp[32] tn[31] tp[29] rp[28] rn[26] avdl tp[28] tn[27] tn[25] rp[24] a w vss vss vss vss nc vss resk vss rn[30] vss tp[31] vss rn[28] vss vddi vss tp[27] tp[25] rn[24] 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 document id: pmc-1991258, issue 7 pin diagram bottom right corner csu _ avdh csu _ avdl rp[8] rn[8] a a csu _ avdl csu _ avdl tn[9] tp[9] a b tn[10] tp[10] tn[11] tp[11] a c vddi tn[12] tp[12] vss a d rp[9] rn[9] avdl vddi a e avdh rp[10] rn[10] vss a f rp[11] rn[11] rp[12] rn[12] a g vddi tn[13] tp[13] vss a h tn[14] tp[14] tn[15] tp[15] aj avdh tn[16] tp[16] vss a k rp[13] rn[13] rp[14] rn[14] a l avdl rp[15] rn[15] vss a m rp[16] rn[16] res resk a n avdh nc nc vss a p vddi tms tck tdi ar rp[23] avdh rp[21] vddi tn[22] avdh vddi vddi rp[17] avdh tn[19] atb1[2] atb0[2] d[7] d[4] d[1] vddo vddo vddo vss a t rn[23] vddi rn[21] tn[23] tp[22] rp[20] avdl rp[18] rn[17] vddi tp[19] tn[17] nc vddi d[5] d[2] vddo vddo vddo vss a u rp[22] avdl tn[24] tp[23] tn[21] rn[20] rp[19] rn[18] tn[20] nc tn[18] tp[17] nc vddi d[3] d[0] vddo vddo vddo vss a v rn[22] vss tp[24] vss tp[21] vss rn[19] vss tp[20] vss tp[18] vss vddi d[6] vddi vddi vss vss vss vss a w 2019181716151413121110987654321
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 document id: pmc-1991258, issue 7 8 pin description table 1 pin description lvds ports (256 signals) pin name type pin no. function rp[1] rn[1] rp[2] rn[2] rp[3] rn[3] rp[4] rn[4] rp[5] rn[5] rp[6] rn[6] rp[7] rn[7] rp[8] rn[8] rp[9] rn[9] rp[10] rn[10] rp[11] rn[11] rp[12] rn[12] rp[13] rn[13] rp[14] rn[14] rp[15] rn[15] rp[16] rn[16] rp[17] rn[17] rp[18] rn[18] rp[19] rn[19] rp[20] rn[20] rp[21] rn[21] rp[22] rn[22] rp[23] rn[23] rp [ 24 ] analog lvds input m4 m3 n3 n2 p2 p1 r3 r2 v4 v3 y2 y1 y4 y3 aa2 aa1 ae4 ae3 af3 af2 ag4 ag3 ag2 ag1 al4 al3 al2 al1 am3 am2 an4 an3 at12 au12 au13 av13 av14 aw14 au15 av15 at18 au18 av20 aw20 at20 au20 a v21 receive serial data. the differential receive serial data links (rp[64:1]/rn[64:1]) carry the receive sonet/sdh sts-12 frame data from upstream sources in bit serial format. each differential pair rp[ x ]/rn[ x ] carries a constituent sts-12 stream. data on rp[ x ]/rn[ x ] is encoded in an 8b/10b format extended from ieee std. 802.3. the 8b/10b character bit ?a? is transmitted first and the bit ?j? is transmitted last. all rp[ x ]/rn[ x ] differential pairs must be frequency locked and phase aligned (within a certain tolerance) to each other. rp[64:1]/rn[64:1] are nominally 777.6 mhz data streams. unused rp[x]/rn[x] pad pairs can be left floating , or can be grounded. in either case the analog blocks (rxlv and the dru) can be disabled to reduce power consumption. tying one pin high and the corresponding pin of an input pair low will apply voltage across the internal termination resistor, which will increase system power consumption.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 document id: pmc-1991258, issue 7 pin name type pin no. function rn[24] rp[25] rn[25] rp[26] rn[26] rp[27] rn[27] rp[28] rn[28] rp[29] rn[29] rp[30] rn[30] rp[31] rn[31] rp[32] rn[32] rp[33] rn[33] rp[34] rn[34] rp[35] rn[35] rp[36] rn[36] rp[37] rn[37] rp[38] rn[38] rp[39] rn[39] rp[40] rn[40] rp[41] rn[41] rp[42] rn[42] rp[43] rn[43] rp[44] rn[44] rp[45] rn[45] rp[46] rn[46] rp[47] rn[47] rp[48] rn[48] rp[49] rn[49] rp[50] rn [ 50 ] aw21 at25 au25 au26 av26 at27 au27 av27 aw27 at31 au31 av31 aw31 au32 av32 at33 au33 ah36 ah37 ag37 ag38 af38 af39 ae37 ae38 ab36 ab37 y38 y39 y36 y37 w38 w39 r36 r37 p37 p38 n36 n37 n38 n39 j36 j37 j38 j39 h37 h38 g36 g37 d28 c28 c27 b27
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 document id: pmc-1991258, issue 7 pin name type pin no. function rp[51] rn[51] rp[52] rn[52] rp[53] rn[53] rp[54] rn[54] rp[55] rn[55] rp[56] rn[56] rp[57] rn[57] rp[58] rn[58] rp[59] rn[59] rp[60] rn[60] rp[61] rn[61] rp[62] rn[62] rp[63] rn[63] rp[64] rn[64] b26 a26 c25 b25 d22 c22 b20 a20 d20 c20 b19 a19 d15 c15 c14 b14 d13 c13 b13 a13 d9 c9 b9 a9 c8 b8 d7 c7 tp[1] tn[1] tp[2] tn[2] tp[3] tn[3] tp[4] tn[4] tp[5] tn[5] tp[6] tn[6] tp[7] tn[7] tp[8] tn[8] tp[9] tn[9] tp[10] tn[10] tp[11] tn[11] tp[12] tn [ 12 ] analog lvds output j2 j3 k1 k2 k3 k4 m1 m2 t1 t2 t3 t4 u2 u3 v1 v2 ab1 ab2 ac3 ac4 ac1 ac2 ad2 a d3 transmit serial data. the differential transmit working serial data links (tp[64:1]/tn[64:1]) carry the transmit sonet/sdh sts-12 frame data to downstream sinks in bit serial format. each differential pair carries a constituent sts-12 stream. data on tp[ x ]/tn[ x ] is encoded in an 8b/10b format extended from ieee std. 802.3. the 8b/10b character bit ?a? is transmitted first and the bit ?j? is transmitted last. all tp[ x ]/tn[ x ] differential pairs are frequency locked and phase aligned (within a certain tolerance) to each other. tp[64:1]/tn[64:1] are nominally 777.6 mhz data streams. unused tp[x]/tn[x] pad pairs can be left unconnected.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 document id: pmc-1991258, issue 7 pin name type pin no. function tp[13] tn[13] tp[14] tn[14] tp[15] tn[15] tp[16] tn[16] tp[17] tn[17] tp[18] tn[18] tp[19] tn[19] tp[20] tn[20] tp[21] tn[21] tp[22] tn[22] tp[23] tn[23] tp[24] tn[24] tp[25] tn[25] tp[26] tn[26] tp[27] tn[27] tp[28] tn[28] tp[29] tn[29] tp[30] tn[30] tp[31] tn[31] tp[32] tn[32] tp[33] tn[33] tp[34] tn[34] tp[35] tn[35] tp[36] tn[36] tp[37] tn[37] tp[38] tn[38] tp [ 39 ] ah2 ah3 aj3 aj4 aj1 aj2 ak2 ak3 av9 au9 aw10 av10 au10 at10 aw12 av12 aw16 av16 au16 at16 av17 au17 aw18 av18 aw22 av22 au23 at23 aw23 av23 av24 au24 av28 au28 au29 at29 aw29 av29 av30 au30 al38 al37 ak39 ak38 ak37 ak36 ah39 ah38 ad39 ad38 ad37 ad36 a c38
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 document id: pmc-1991258, issue 7 pin name type pin no. function tn[39] tp[40] tn[40] tp[41] tn[41] tp[42] tn[42] tp[43] tn[43] tp[44] tn[44] tp[45] tn[45] tp[46] tn[46] tp[47] tn[47] tp[48] tn[48] tp[49] tn[49] tp[50] tn[50] tp[51] tn[51] tp[52] tn[52] tp[53] tn[53] tp[54] tn[54] tp[55] tn[55] tp[56] tn[56] tp[57] tn[57] tp[58] tn[58] tp[59] tn[59] tp[60] tn[60] tp[61] tn[61] tp[62] tn[62] tp[63] tn[63] tp[64] tn[64] ac37 ab39 ab38 v39 v38 u37 u36 u39 u38 t38 t37 m38 m37 l37 l36 l39 l38 k38 k37 b31 c31 a30 b30 c30 d30 a28 b28 a24 b24 c24 d24 b23 c23 a22 b22 a18 b18 c17 d17 a17 b17 b16 c16 b12 c12 c11 d11 a11 b11 b10 c10
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 document id: pmc-1991258, issue 7 table 2 pin description tse control and clocking (5 signals) pin name type pin no. function sysclk input b5 system clock. the system clock signal (sysclk) is the master clock for the tse device. sysclk must be a 77.76 mhz clock, with a nominal 50% duty cycle. rj0fp input c5 receive serial interface frame pulse. the receive serial interface frame pulse signal (rj0fp) provides system timing for the receive serial interface. rj0fp is supplied in common to all devices in a system containing one or more tse devices. rj0fp is set high once every 9720 sysclk cycles, or multiple thereof. a software configurable delay from rj0fp is used to indicate that the j0 frame boundary 8b/10b characters have been delivered on all the receive serial data links (rp[64:1]/rn[64:1]) and are ready for processing by the time-space-time switching elements. rj0fp is sampled on the rising edge of sysclk. tj0fp output g2 transmit serial interface frame pulse. the transmit serial interface frame pulse signal (tj0fp) should be treated as an asynchronous output which can be used to give a rough estimate of when the j0 character is transmitted on the serial telecombus. tj0fp is set high once every 9720 sysclk cycles. the pulse timing relative to the sts-12 frame is determined by the tj0dly register. it is recommended that the register is set so the tj0fp pulse indicates that the j0 frame boundary 8b/10b character has been serialised out on all the transmit serial data links (tp[64:1]/tn[64:1]). tj0fp is for diagnostic purposes only and is not intended as a reference for timing. cmp input e4 connection memory page. the transmit connection memory page select signal (cmp) controls the selection of the connection memory page in tse. in each block with connection memory, cmp is xored with a software configurable page select bit. when the result is high, connection memory page 1 is selected. when the result is low, connection memory page 0 is selected. cmp is sampled on the rising edge of sysclk at the rj0fp frame position. refer to cmp functional timing for an indication of when a change to cmp takes effect. rstb input au35 reset enable bar. the active low reset signal (rstb) provides an asynchronous reset for the tse. rstb is a schmitt triggered input with an integral pull-up resistor. table 3 pin description microprocessor interface (34 signals) pin name type pin no. function csb input e3 chip select bar. the active low chip select signal (csb) controls microprocessor access to registers in the tse device. csb is set low during tse microprocessor interface port register accesses. csb is set high to disable microprocessor accesses. if csb is not required (i.e. register accesses controlled using rdb and wrb signals only), csb should be connected to an inverted version of the rstb input. rdb input f2 read enable bar. the active low read enable bar signal (rdb) controls microprocessor read accesses to registers in the tse device. rdb is set low and csb is also set low durin g tse micro p rocessor interface port
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 document id: pmc-1991258, issue 7 pin name type pin no. function register read accesses. the tse drives the d[15:0] bus with the contents of the addressed register while rdb and csb are low. wrb input f4 write enable bar. the active low write enable bar signal (wrb) controls microprocessor write accesses to registers in the tse device. wrb is set low and csb is also set low during tse microprocessor interface port register write accesses. the contents of d[15:0] are clocked into the addressed register on the rising edge of wrb while csb is low. d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o an36 an39 ap37 ap36 ap38 ar37 ar36 ar38 at7 aw7 au6 at6 av6 au5 at5 av5 microprocessor data bus. the bi-directional data bus, d[15:0] is used during tse microprocessor interface port register reads and write accesses. d[15] is the most significant bit of the data words and d[0] is the least significant bit. a[12]/trs a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] input a5 b33 a33 d34 b34 a34 c35 b35 a35 e39 e38 e36 e37 microprocessor address bus. the microprocessor address bus (a[12:0]) selects specific microprocessor interface port registers during tse register accesses. a[12] is also the test register select (trs) address pin and selects between normal and test mode register accesses. trs is set high during test mode register accesses, and is set low during normal mode register accesses. ale input f3 address latch enable. the address latch enable signal (ale) is active high and latches the address pins (a[12:0]) when it is set low. the internal address latches are transparent when ale is set high. ale allows the tse to interface to a multiplexed address/data bus. ale has an integral pull-up resistor. intb open drain output g1 interrupt request bar . the active low interrupt enable signal (intb) output goes low when an tse interrupt source is active and that source is unmasked. intb returns high when the interrupt is acknowledged via an appropriate register access. intb is an open drain output.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 document id: pmc-1991258, issue 7 table 4 pin description jtag port (5 signals) pin name type pin no. function tck input ar2 test clock. the jtag test clock signal (tck) provides timing for test operations that are carried out using the ieee p1149.1 test access port. tms input ar3 test mode select. the jtag test mode select signal (tms) controls the test operations that are carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull- up resistor. tdi input ar1 test data input. the jtag test data input signal (tdi) carries test data into the tse via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. a 30 kohm external pull-up resistor is recommended on this pin. tdo tri-state e2 test data output. the jtag test data output signal (tdo) carries test data out of the tse via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is inactive except when scanning of data is in progress. trstb input av35 test reset bar. the active low jtag test reset signal (trstb) provides an asynchronous tse test access port (tap) controller reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull-up resistor. the tap controller must be placed in the test-logic-reset state after applying power to the device to guarantee correct device operation. this is easily accomplished by connecting trstb to the rstb input and performing a device reset, but is not necessary if another method of resetting the tap controller is implemented. table 5 pin description external resistors (8 signals) pin name type pin no. function res[4] res[3] res[2] res[1] analog input b7 g38 av33 an2 reference resistor connection. an off-chip 3.16k 1% resistor is connected between each positive resistor reference pin res[i] and the corresponding kelvin ground contact resk[i]. resk[4] resk[3] resk[2] resk[1] analog input a7 g39 aw33 an1 reference resistor connection. an off-chip 3.16k 1% resistor is connected between each positive resistor reference pin res[i] and the corresponding kelvin ground contact resk[i]. table 6 pin description analog test bus (8 signals) pin name type pin no. function atb0[4] atb0[3] atb0[2] atb0[1] analog d32 am36 at8 h4 these pins are used for pmc testing only and should be directly connected to ground. atb1[4] analog d31 these pins are used for pmc testing only and should be directly connected
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 document id: pmc-1991258, issue 7 pin name type pin no. function atb1[3] atb1[2] atb1[1] al36 at9 j4 to ground. pin description digital core power (56 signals) pin name type pin no. function vddi[55:0] power a15 a32 aa37 ac36 ad4 ae1 af36 ag36 ah4 aj37 am39 an37 an38 ap39 ar39 ar4 at13 at14 at17 at24 at28 at35 au11 au19 au7 av7 aw25 aw5 aw6 aw8 c21 c29 c33 c34 d12 d16 d23 d26 d27 d33 d35 d5 e1 f1 f38 the digital core power pins (vddi[55:0]) should be connected to a well- decoupled +1.8 v dc supply.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 document id: pmc-1991258, issue 7 pin name type pin no. function g3 g4 h1 l3 m36 n4 p4 r39 t36 u4 w3 table 7 pin description digital i/o power (36 signals) pin name type pin no. function vddo[35:0] power at2 at3 at36 at37 at38 at4 au4 au3 au36 au37 au38 au2 av2 av3 av36 av37 av38 av4 b2 b3 b36 b37 b38 b4 c2 c3 c36 c37 c38 c4 d2 d3 d36 d37 d38 d4 the digital i/o power pins (vddo[35:0]) should be connected to a well- decoupled +3.3 v dc supply.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 document id: pmc-1991258, issue 7 table 8 pin description analog low voltage power (28 signals) pin name type pin no. function csu_avdl[1 1:0] power aa3 ab3 ab4 at22 au21 au22 c18 c19 d18 v36 v37 w37 the csu analog power pins (csu_avdl[11:0]) should be connected to a +1.8 v dc supply. see filtering recommendations in section 15.3. note that the csu_avdl is included in references to avdl throughout this document unless otherwise noted. avdl[15:0] power aa38 ae2 af37 am4 at32 au14 av19 av25 b15 b21 c26 d8 h36 p3 r38 w2 the analog power pins (avdl[27:0]) should be connected to a +1.8 v dc supply. see filtering recommendations in section 15.3. note that the csu_avdl is included in references to avdl throughout this document unless otherwise noted. table 9 pin description analog power pin name type pin no. function avdh[23:0] power aa36 ae36 af4 aj36 ak4 ap4 at11 at15 at19 at26 at30 at34 d10 d14 d21 d25 the analog power pins (avdh[23:0]) should be connected to a +3.3v dc supply. see filtering recommendations in section 15.3. note that the csu_avdh is included in references to avdh throughout this document unless otherwise noted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 document id: pmc-1991258, issue 7 pin name type pin no. function d29 d6 f36 k36 l4 p36 r4 w4 csu_avdh [4:1] power aa4 at21 d19 w36 the csu analog power quiet pins (csu_avdh[4:1]) should be connected to a +3.3v dc supply. see filtering recommendations in section 15.3. note that the csu_avdh is included in references to avdh throughout this document unless otherwise noted. table 10 pin description ground (76 signals) pin name type pin no. function vss[75:0] ground w1 u1 t39 r1 p39 n1 m39 l1 k39 j1 h39 f39 d39 d1 c39 c1 b39 b1 aw9 aw4 aw39 aw38 aw37 aw36 aw34 aw32 aw30 aw3 aw28 aw26 aw24 aw2 aw19 aw17 a w15 the ground pins (vss[75:0]) should be connected to gnd.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 document id: pmc-1991258, issue 7 pin name type pin no. function aw13 aw11 aw1 av39 av1 au39 au1 at39 at1 ap1 am1 al39 ak1 aj39 ah1 ag39 af1 ae39 ad1 ac39 aa39 a8 a6 a4 a39 a38 a37 a36 a31 a3 a29 a27 a25 a23 a21 a2 a16 a14 a12 a10 a1 table 11 pin description no connect (20 signals) pin name type pin no. function nc[19:0] aj38 am37 am38 ap2 ap3 au34 a u8 the no connect pins (nc[19:0]) should be left floating.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 document id: pmc-1991258, issue 7 pin name type pin no. function av11 av34 av8 aw35 b29 b32 b6 c32 c6 f37 h2 h3 l2 total pins all pin description tables: 560 notes on pin descriptions 1. all inputs and bi-directionals present minimum capacitive loading. all non-lvds inputs and bi-directionals except schmitt trigger inputs (rstb, trstb and sysclk) operate at ttl logic levels 2. inputs rstb, ale, tms and trstb have internal pull-up resistors. 3. all outputs except the lvds links have 8ma drive capability ? this includes tj0fp, tdo, intb and d[15:0]). 4. the vddi, avdl, and csu_avdl power pins are not internally connected to each other. failure to connect these pins externally may cause malfunction or damage to the tse. similarly, the vddo, avdh, and csu_avdh power pins must be connected externally to avoid device malfunction or damage. 5. the vddi, vddo, avdh, avdl, csu_avdh, and cs u_avdl power pins all share a common ground.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 document id: pmc-1991258, issue 7 9 functional description 9.1 lvds overview the lvds family of cells allow the implementation of 777.6 mb/s lvds links. a reference clock of 77.76mhz is required. four 777.6 mb /s lvds links form a high-speed serial telecombus interface for passing an sts-48 aggregate data stream. a generic lvds link according to ieee 1596.3-1996 is illustrated in figure 7. the transmitter drives a differential signal through a pair of 50 characteristic interconnects, such as board traces, backplane traces, or short lengths of cable. the receiver presents a 100 differential termination impedance to terminate the lines. included in the standard is sufficient common- mode range for the receiver to accommodate as much as 925mv of common-mode ground difference. figure 7 generic lvds link block diagram complete serdes transceiver functionality is provided. ten-bit parallel data is sampled by the line rate divided-by-10 clock (77.76mhz sysclk) and then serialized at the line rate on the lvds output pins by a 777.6mhz clock synthesize d from sysclk. serial line rate lvds data is sampled and de-serialized to 10-bit parallel data. parallel output transfers are synchronized to a gated line rate divided-by-10 clock. the gating duty cycle is adjusted such that the throughput of the parallel interface equals the receive input data rate. it is expected that the clock source of the transmitter is the same as the clock source of the receiver to ensure the data throughput at both ends of the link are identical.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 document id: pmc-1991258, issue 7 data is guaranteed to contain sufficient transition density to allow reliable operation of the data recovery units by 8b/10b block coding and decoding provided by the t8de and r8fa blocks. at the system level, reliable operation will be obtained if proper signal integrity is maintained through the signal path and the receiver requirements are respected. specifically, a worst case eye opening of 0.7ui and 100mv differential amplitude is needed. these conditions should be achievable with a system architecture consisting of board traces, two sets of backplane connectors and up to 1m of backplane interconnects. this assumes proper design of 100 differential lines and minimization of discontinuities in the signal path. due to power constraints, the output differential amplitude is approximately 350mv. the lvds system is comprised of the lvds receiver (rxlv), lvds transmitter (txlv), transmitter reference (txref), data recovery uni t (dru), parallel to serial converter (piso), and clock synthesis unit (csu). 9.1.1 lvds receiver (rxlv) the rxlv block is a 777.6 mb/s low voltage differential signaling (lvds) receiver according to the ieee 1596.3-1996 lvds specification. the rxlv block is the receiver in figure 7, accepting up to 777.6 mb/s lvds signals from the transmitter, over rp[x]/rn[x] pins, amplifying them and converting them to digital signals, then passing them to a data recovery unit (dru). holding to the ieee 1596.3-1996 specification, the rxlv has a differential input sensitivity better than 100mv, with no hysteresis. these are lvds receivers not cmos. if a link is unused there is no electrical problem in leaving rp/rn floating (as opposed to a cmos input). power dissipation is the same regardless of whether the input is connected or not. no damage to the device will occur. unused links should be disabled in software. in th is case the power for that link will be nearly 0mw. there is no requirement for how quickly this should be done. it simply results in lower power dissipation since circuitry will be shut down. this is not mandatory for the device to operate properly but is a good practice since it improves margins. hot-swapping is supported. the channel can be left enabled at all time and the device will sync up once the far end transmitter is connected. there will be no effect on other channels. there are 64 instances of the rxlv block on the tse. 9.1.2 lvds transmitter (txlv) the txlv block is a 777.6 mbit/s low voltage differential signaling (lvds) transmitter according to the ieee 1596.3-1996 lvds specification. the txlv accepts 777.6 mbit/s differential data from a ?parallel-in, serial-out? (piso) circuit and then transmits the data off-chip as a low voltage differential signal on tp[x]/tn[x] pins.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 document id: pmc-1991258, issue 7 the txlv uses a reference current and voltage from the txlvref block to control the output differential voltage amplitude and the output common-mode voltage. unused links should be disabled in software. in th is case the power for that link will be nearly 0mw. there is no requirement for how quickly this should be done. it simply results in lower power dissipation since circuitry will be shut down. this is not mandatory for the device to operate properly but is a good practice since it improves margins. hot-swapping is supported. the channel can be left enabled at all time and the device will sync up once the far end receiver is connected. there will be no effect on other channels. there are 64 instances of the txlv block on the tse. 9.1.3 lvds transmit reference (txref) the txlvref provides an on-chip bandgap voltage reference (1.20v 5%) and a precision current to the txlv (777.6 mb/s lvds transmitter) block?s. the reference voltage is used to control the common-mode level of the txlv output, while the reference current is used to control the output amplitude. the precision currents are generated by forcing the reference voltage across an external, off-chip 3.16k (1%) resistor. the resulting current is then mirrored through several individual reference current outputs, so each txlv receives its own reference current. there are four instances of the txref on the tse. 9.1.4 data recovery unit (dru) the dru is a fully integrated data recovery and serial to parallel converter that can be used for 777.6 mb/s nrz data. 8b/10b block code is used to guarantee transition density for optimal performance. the dru recovers data and outputs a 10-bit word synchronized with a line rate divided-by-10 gated clock to allow frequency deviations between the data source and the local oscillator. the output clock is not a recovered clock. the dr u accumulates 10 data bits and outputs them on the next clock edge. if 10 bits are not available for transfer at a given clock cycle, the output clock is gated. the dru provides moderate high frequency jitter tolerance suitable for inter-chip serial link applications. it can support frequency deviations up to 100ppm. there are 64 instances of the dru on the tse.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 document id: pmc-1991258, issue 7 9.1.5 parallel to serial converter (piso) the piso_1250 is a parallel-to-serial converter designed for high-speed transmit operation, supporting up to 777.6 mb/s. there are 64 instances of the piso on the tse. 9.1.6 clock synthesis unit (csu) the csu is a fully integrated clock synthesis unit. it generates low jitter multi-phase differential clocks at 777.6 mhz for use by the transmitter. there are 4 instances of the csu on the tse. 9.2 receive 8b/10b frame aligner (r8fa) the r8fa block performs 8b/10b character a lignment and sonet sts-12 frame alignment on an unaligned bit stream received from a dru block. a total of 64 r8fa blocks are instantiated in the tse device. r8fas recovers 8b/10b character alignment by searching for the 8b/10b j0 frame alignment control character, which is used to identify the start of sts-12 flows. in addition, the tse?s sts-1 switching mechanism requires that all incoming sts-12s be mutually aligned within a certain tolerance. the 64 r8fas in each tse must present frame aligned 10b samples of aligned sts-12 flows to the switching stages. the r8fa contains a fifo to accommodate jitter, wander, and phase alignment differences between the timing domain of the receive lvds links and the system clock timing domain. the fifo also enables alignment of the multiple r8 fas in transmitting frames to the switching blocks. table 12 show the 8b/10b characters that the r8fa recognizes. all 8b/10b characters in table 12 are reserved for telecombus control characters. the tse doesn?t do any processing on the telecombus control characters (with the exception of k28.5). the tse will accepts incorrect disparity characters without signaling lcvs for those characters noted in the table. table 12 telecombus control characters code group name curr. rd- abcdei fghj curr. rd+ abcdei fghj signal description disparity violation allowed k28.5 001111 1010 110000 0101 transport j0 frame alignment no k28.0- 001111 0100 - high-order path h3 byte, no negative justification event yes k28.0+ - 110000 1011 high-order path pso byte, positive yes
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 document id: pmc-1991258, issue 7 code group name curr. rd- abcdei fghj curr. rd+ abcdei fghj signal description disparity violation allowed justification event k.28.4- 001111 0010 - high-order path ais yes k28.6 001111 0110 110000 1001 high-order path j1 frame alignment no k27.7- 110110 1000 low order path frame alignment #1 yes k27.7+ 001001 0111 low order path frame alignment #2 yes k28.7- 001111 1000 low order path frame alignment #3 yes k28.7+ 110000 0111 low order path frame alignment #4 yes k29.7- 101110 1000 low order path frame alignment #5 yes k29.7+ 010001 0111 low order path frame alignment #6 yes k30.7- 011110 1000 low order path frame alignment #7 yes k30.7+ 100001 0111 low order path frame alignment #8 yes k23.7 111010 1000 000101 0111 non low-order path payload overhead bytes (rsoh, msoh, poh, r, v1, v2, v3, v4) no k.28.4+ - 110000 1101 low-order path ais yes microprocessor access to the r8fa allows the control and monitoring of its activities. character and frame alignment status can be forced and monitored. 8b/10b line code violations are monitored in a performance monitor counter. lcv propagation is software configurable. lcvs are either mapped to a valid characters (d12.3) or forced to an lcv on the transmit link. fifo errors due to improper rj0dly setting can also be monitored. the r8fa also provides reset, enable and test control over its associated dru and rxlv analog blocks. 9.2.1 character alignment the character alignment sub-block locates charac ter boundaries in the incoming 8b/10b data stream. the aligner logic may be in one of two states, sync state and hunt state. it uses the 8b/10b j0 frame alignment control character (k28.5+, k28.5-) used to encode the sonet/sdh j0 byte to locate character boundaries and to enter the sync state. it monitors the receive data stream for line code violations (lcv). an lcv is declared when the running disparity of the receive data is not consistent with the previous character or the data is not one of the characters defined in ieee std. 802.3. the character alignment sub-block recognizes an extended set of 8b/10b control characters. the character decode block permits running disparity vi olations for these specific codes (as shown in table 2): k28.0-, k28.0+, k28.4-, k28.4+, k27.7-, k27.7+, k 28.7-, k28.7+, k29.7-, k29.7+, k30.7-, k30.7+. excessive lcvs are used to transition the character alignment logic to the hunt state.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 document id: pmc-1991258, issue 7 normal operation occurs when the character alignm ent sub-block is in the sync state. 8b/10b characters are written to the fifo using the character alignment of the k28.5 character that caused entry to the sync state. mimic k28.5 ch aracters at other alignments are ignored. the receive data is constantly monitored for line code violations. if 5 or more lcvs are detected in a window of 15 characters, the character alignment sub- block transitions to the hunt state. it will search all possible alignments in the receive data for the k28.5 character. in the mean time, the original character alignment is maintained until a k28.5 character is found. at that point, the character alignment is moved to this new location and the sub-block transitions to the sync state. 9.2.2 frame alignment the frame alignment sub-block monitors the data from the character aligner sub-block for the j0 byte. an out of position j0 counter counts k28.5 characters that are out of position. the state of this counter conditions transitions in and out of the aligned state. the block will frame align on the datastream if all the following conditions are satisfied: 1. there are two k28.5 characters in the data stream separate by 9720 sysclk cycles (125.0 us) 2. the r8fa was character aligned throughout that 125.0 us period 3. the out of position j0 counter is not = 3. note that when out of frame alignment, this counter is cleared by 2 k28.5 characters se parated by 125.0 us. so if this counter was 3, then the first 2 properly spaced k28.5 characters will clear the counter, and a third properly spaced k28.5 will satisfy condition 1. frame alignment is lost when either: 1. the block is forced out of frame alignm ent via software via the r8fa control and status fofa register bit. 2. the r8fa loses character alignment (either due to software control or the 5 lcvs within 15 characters). 3. an out of position j0 count of 3 is reached.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 document id: pmc-1991258, issue 7 the out of position j0 counter is incremented for each k28.5 character it encounters that is out of position with respect to the current frame alignmen t. the counter saturates at 3. when the block is frame aligned, the counter is cleared by an in position k28.5 character. when the block is not aligned, the counter is cleared by the next occurrence of next 2 k28.5 characters appearing separated by 125.0 us. 9.2.3 fifo buffer the fifo buffer sub-block provides isolation between the timing domain of the associated receive lvds link and that of the system cl ock (sysclk). aligned 8b/10b characters are written into a 10-bit by 24-word deep fifo at the line clock rate. data is read from the fifo at every sysclk cycle. 9.2.4 frame counter the frame counter sub-block keeps track of the octet identity of the outgoing data stream. it is initialized by a delayed version of the rj0fp signal. it adjusts the read pointer so the j0 byte location in the fifo is sampled at specific device wide event. all r8fas are then aligned to transmit their j0 byte at this event. 9.3 ingress time switch element (itse) the itse accepts sts-12-aligned cyclic groups of twelve sts-1 samples over twelve time steps from the r8fas, and distributes these samples in an arbitrary time permutation to the space switch stage. the time permutation is determin ed by the contents of two switching control register sets or pages, each of which describe s which sts-1 sample should be output during the i th (1 <= i <=12) sts-1 time slot. these control registers are accessible via the microprocessor bus. selection of the switching page is determined by the device cmp pin, and on a per itse basis through the microprocessor control interface. the itse can also be set in a bypass mode in which no switching is done. when in bypass mode, the latency of the itse is the same as when it is in dynamic (switching) mode. the itse is implemented as 2x12 sts-1 buffers, one to accumulate the incoming stream and the other to accept twelve sts-1s in parallel and then deliver these samples in the order specified by the switching control registers. 9.4 space switch stage (sswt) the sswt accepts fully aligned sts-12 streams from ingress time stages at 77.76 mhz. the space stage implements a space switch for each of the twelve times in the cyclic sts-12 time structure, and delivers the sts-1 samples to the intended egress lvds stages.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 document id: pmc-1991258, issue 7 the sswt is equivalent to a crossbar, with separate switch settings taken from control tables for each egress channel for each 8b/10b time period (77.76 mhz). multicast is supported by permitting any number of output columns to take a sample from any input row at the same time. the sswt contains two sets or pages of control registers to control the switching function. each set of control registers consists of twelve registers (one per time step) of six bits (to select among 64 sources) for each of 64 egress ports. these registers are accessible from the microprocessor interface; they constitute 2*12*6*64 = 9216 bits. selection of the switching page is determined by the device cmp pin, or through the microprocessor control interface. another control register in the sswt allows specification of the delay between the system synchronization pulse and j0 arrivals at the tse receive analog blocks. the sswt is implemented by a set of input-selector muxes at each output. 9.5 egress time switch element (etse) the etse accepts sts-12-aligned cyclic groups of twelve sts-1 samples over twelve time steps from the space switch, and outputs these samples in an arbitrary time permutation to the egress ports. the time permutation is determined by th e contents of two switching control register sets or pages, each of which describes which sts-1 sample should be output during the ith (1 <= i <=12) sts-1 time slot. these control registers are accessible via the microprocessor bus. selection of the switching page is determined by the device cmp pin, and on a per etse basis through the microprocessor control interface. the etse can also be set in a bypass mode in which no switching is done. when in bypass mode, the latency of the etse is the same as when it is in dynamic (switching) mode. the egress time stage is implemented as two 12 sts-1 buffers, one to accumulate the incoming stream and the other to accept twelve sts-1s in parallel and then deliver these samples in the order specified by the switching control settings. 9.6 transmit 8b/10b di sparity encoder (t8de) the t8de block corrects the running disparity of an 8b/10b character stream and buffers data in a fifo before transmission to the piso block. a total of 64 t8de blocks are instantiated in the tse device. the input data to the t8de blocks originated from the r8fa blocks at which point they have correct running disparity. however, due to the time and space re-arrangement activities of the tse, the running disparity is no longer consistent. the t8de block inverts the 6b and 4b sub- characters to ensure correct running disparity.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 document id: pmc-1991258, issue 7 the t8de will not correct running disparity violations for these specific codes: k28.0-, k28.0+, k28.4-, k28.4+, k27.7-, k27.7+, k 28.7-, k28.7+, k29.7-, k29.7+, k30.7-, k30.7+, k23.7-, k23.7+. the timing of egress lvds signals requires that this block include a fifo to cross from the internal tse time domain to the time domain of the egress lvds units. the clocks driving these two domains originate in the same master clock, but may have varying skew. microprocessor access to the t8de allows the co ntrol and monitoring of its activities. fifo status can be monitored and corrected. the t8de can be configured to insert j0s into the datastream. the t8de also provides reset, enable and test control over its associated piso and txlv analog blocks. 9.7 clock synthesis and transmit reference digital wrapper (cstr) the cstr is an digital wrapper for the csu and txref lvds analog locks. it provides microprocessor access for resetting and disabling the csu. it also monitors the lock state of the csu on the system clock. 9.8 fabric latency the flow of sts-1 samples from ingress lvds to egress lvds has variable latency, depending on the timing of the arriving lvds stream, and the clock variation on the egress lvds drivers. a reasonable estimate of the tse?s latency can be arrived at by making assumptions about the depths of the receive and transmit fifos: we assume the ?j0? timing is set to maintain about 12 samples in the ingress fifo; the egress fifo is designed to be centered at 4 samples ? so typically delay due to fifos will be 16 clock cycles. maximum delay through the fifos can be 32 cycles. the r8fa imposes an additional 6 cycles of latency in addition to the ingress fifo delay. the t8de imposes 4 cycles of latency in addition to the egress fifo delay. the latency through the time and space switch stages is 32 cycles. data latency through the analog blocks is around 90 ns or 7 clock cycles with 5 cycles de lay through the rx analog blocks and 2 cycles delay through the transmit analog blocks. by summing all the delays the typical latency of the tse is 65 clock cycles or 836 ns. with worst case conditions in both fifos, latency rises to 81 clock cycles or 1044 ns. 9.9 jtag support the tse provides jtag support for testing device interconnection on a pc board.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 document id: pmc-1991258, issue 7 9.10 microprocessor interface the microprocessor interface block provides the logic required to interface the normal mode and test mode registers within the tse to a generic microprocessor bus. the normal mode registers are used during normal operation to configure and monitor the tse. the register set is accessed as shown in the register memory map table below. addresses that are not shown are not used and must be treated as reserved. the ports are organized into 16 port sets. a port register set is specified for each port set. registers for port register set 1 are specified in the register memory map. for the remaining port register sets, only the range of registers is specified. as with port register set 1 not all addresses within a range correspond to actual registers. to obtain a corresponding register for port set n+1, take the register address for port register set 1 and replace address bits a[11:8] with n. the grouping of the receive and transmit lvds ports to a port register set is defined as follows: port register set n+1 controls blocks associated with receive lvds links rp[4n+4:4n+1]/rn[4n+4:4n+1]. this includes rxlv, dru, and r8fa blocks 4n+4 down to 4n+1, and itse block n+1. port register set n+1 controls blocks associated with transmit lvds links tp[4n+4:4n+1]/tn[4n+4:4n+1]. th is includes etse block n+1, t8de, piso, and txlv blocks 4n+4 down to 4n+1. register memory map address register 0000 tse master reset 0001 tse master clock activity and accumulation trigger 0002 tse master configuration 0003 tse master interrupt block identifier 0004 tse master r8fa interrupt source #1 0005 tse master r8fa interrupt source #2 0006 tse master r8fa interrupt source #3 0007 tse master r8fa interrupt source #4 0008 tse master t8de interrupt source #1 0009 tse master t8de interrupt source #2 000a tse master t8de interrupt source #3 000b tse master t8de interrupt source #4 000c tse master itse interrupt source 000d tse master etsi interrupt source 000e tse master cstr interrupt source 000f tse master user defined 0010 tse master jtag id high 0011 tse master jtag id low
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 document id: pmc-1991258, issue 7 address register 0012-001f reserved 0020 cstr #1 control 0021 cstr #1 interrupt enable and csu lock status 0022 cstr #1 interrupt indication 0023 cstr #1 reserved 0024 cstr #2 control 0025 cstr #2 configuration and status 0026 cstr #2 interrupt status 0027 cstr #2 reserved 0028 cstr #3 control 0029 cstr #3 configuration and status 002a cstr #3 interrupt status 002b cstr #3 reserved 002c cstr #4 control 002d cstr #4 configuration and status 002e cstr #4 interrupt status 002f cstr #4 reserved 0030-003f reserved 0040 sswt rj0fp delay 0041 sswt indirect control address 0042 sswt indirect control data 0043 sswt interrupt enable 0044 sswt interrupt status 0045-0046 sswt reserved 0047 sswt tj0fp delay 0048 ? 007f reserved 0080-00ff port register set 1 ? ports 1-4 0080 port register set 1: r8fa #1 control and status 0081 port register set 1: r8fa #1 interrupt status 0082 port register set 1: r8fa #1 lcv count 0083 port register set 1: rxlv #1 and dru #1 control 0084 ? 0087 port register set 1: reserved 0088 port register set 1: r8fa #2 control and status 0089 port register set 1: r8fa #2 interrupt status 008a port register set 1: r8fa #2 lcv count 008b port register set 1: rxlv #2 and dru #2 control 008c ? 008f port register set 1: reserved
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 document id: pmc-1991258, issue 7 address register 0090 port register set 1: r8fa #3 control and status 0091 port register set 1: r8fa #3 interrupt status 0092 port register set 1: r8fa #3 lcv count 0093 port register set 1: rxlv #3 and dru #3 control 0094 ? 0097 port register set 1: reserved 0098 port register set 1: r8fa #4 control and status 0099 port register set 1: r8fa #4 interrupt status 009a port register set 1: r8fa #4 lcv count 009b port register set 1: rxlv #4 and dru #4 control 009c ? 009f port register set 1: reserved 00a0 port register set 1: itse #1 indirect address 00a1 port register set 1: itse #1 indirect data 00a2 port register set 1: itse #1 configuration 00a3 port register set 1: itse #1 interrupt status 00a4 ? 00a7 port register set 1: reserved 00a8 port register set 1: etse #1 indirect address 00a9 port register set 1: etse #1 indirect data 00aa port register set 1: etse #1 configuration 00ab port register set 1: etse #1 interrupt status 00ac ? 00af port register set 1: reserved 00b0 port register set 1: t8de #1 control and status 00b1 port register set 1: t8de #1 interrupt status 00b2 ? 00b3 port register set 1: t8de #1 reserved 00b4 port register set 1: t8de #1 test pattern 00b5 port register set 1: txlv #1and piso #1 control 00b6-00b7 port register set 1: reserved 00b8 port register set 1: t8de #2 control and status 00b9 port register set 1: t8de #2 interrupt status 00ba ? 00bb port register set 1: t8de #2 reserved 00bc port register set 1: t8de #2 test pattern 00bd port register set 1: txlv #2 and piso #2control 00be- 00bf port register set 1: reserved 00c0 port register set 1: t8de #3 control and status 00c1 port register set 1: t8de #3 interrupt status 00c2 ? 00c3 port registers set 1: t8de #3 reserved 00c4 port register set 1: t8de #3 test pattern 00c5 port register set 1: txlv #3 and piso #3 control
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 document id: pmc-1991258, issue 7 address register 00c6-00c7 port register set 1: reserved 00c8 port register set 1: t8de #4 control and status 00c9 port register set 1: t8de #4 interrupt status 00ca ? 00cb port register set 1: t8de #4 reserved 00cc port register set 1: t8de #4 test pattern 00cd port register set 1: txlv #4 and piso #4 control 00ce ? 00ff port register set 1: reserved 0100-017f reserved 0180-01ff port register set 2? ports 5-8 0200-027f reserved 0280-02ff port register set 3? ports 9-12 0300-037f reserved 0380-03ff port register set 4? ports 13-16 0400-047f reserved 0480-04ff port register set 5? ports 17-20 0500-057f reserved 0580-05ff port register set 6? ports 21-24 0600-067f reserved 0680-06ff port register set 7? ports 25-28 0700-077f reserved 0780-07ff port register set 8? ports 29-32 0800-087f reserved 0880-08ff port register set 9? ports 33-36 0900-097f reserved 0980-09ff port register set 10? ports 37-40 0a00-0a7f reserved 0a80-0aff port register set 11? ports 41-44 0b00-0b7f reserved 0b80-0bff port register set 12? ports 45-48 0c00-0c7f reserved 0c80-0cff port register set 13? ports 49-52 0d00-0d7f reserved 0d80-0dff port register set 14? ports 53-56 0e00-0e7f reserved 0e80-0eff port register set 15? ports 57-60 0f00-0f7f reserved 0f80-0fff port register set 16? ports 61-64
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 document id: pmc-1991258, issue 7 address register 1000 ? 1fff reserved for test notes on register memory map: 1. for all register accesses, csb must be set low. 2. addresses that are not shown must be treated as reserved. 3. a[12] is the test resister select (trs) and should be set to logic 0 for normal mode register access.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 document id: pmc-1991258, issue 7 10 normal mode register description normal mode registers are used to configure and monitor the operation of the tse. normal mode registers (as opposed to test mode registers) are selected when trs (a[12]) is low. notes on normal mode register bits: 1. unused bits have no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. writeable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 3. writing into read-only normal mode register bit locations does not affect tse operation unless otherwise noted. 4. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the tse operates as intended, reserved register bits must only be written with the logic level as specified. writing to reserved registers should be avoided.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 document id: pmc-1991258, issue 7 register 0000h: tse master reset, identity bit type function default bit 15 r/w dreset 0 bit 14 r/w areset 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register allows separate software reset of digital and analog circuitry on the tse. areset the areset bit allows the analog circuitry in the tse to be reset under software control. if the areset bit is a logic one, all the tse analog circuitry is held in reset. areset must be held at logic 1 for at least 100us to ensure correct reset of the csu. this bit is not self- clearing. therefore, a logic zero must be written to bring the tse out of reset. holding the tse in a reset state places it into a low power, analog stand-by mode. a hardware reset clears the areset bit, thus negating the analog software reset. dreset the dreset bit allows the digital circuitry in the tse to be reset under software control. if the dreset bit is a logic one, all the tse digital circuitry is held in reset. this bit is not self-clearing. therefore, a logic zero must be written to bring the tse out of reset. holding the tse in a reset state places it into a low power, digital stand-by mode. a hardware reset clears the dreset bit, thus negating the digital software reset.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 document id: pmc-1991258, issue 7 register 0001h: tse master clock activity and accumulation trigger bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r tip x bit 0 r sysclka x this register provides activity monitoring on the sy sclk tse input. writing to this register also initiates a transfer of counts from the performance monitor accumulation registers to holding registers where they can be read. the counters themselves are then cleared to begin accumulating events for a new accumulation interval. to prevent saturation of counters, accumulation intervals should be regular. the bits in this register are not affected by write accesses. sysclka the sysclk active (sysclka) bit monitors for low to high transitions on the sysclk clock input. sysclka is set high on a rising edge of sysclk, and is set low when this register is read. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read periodically to detect stuck at conditions.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 document id: pmc-1991258, issue 7 tip the transfer in progress (tip) initiates and monitors the state of r8fa lcv count performance meter register transfers. writing (any value) to this register initiates a device- wide accumulation interval transfer and loads all the performance meter registers in the tse. tip is set to logic one while the transfer is in progress, and is set to a logic zero when the transfer is complete. also if individual performance meter register transfers are initiated (by writing directly to the individual register), tip will monitor the state of those transfers as well. tip can be polled by a microprocessor to determine when the accumulation interval transfer is complete.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 document id: pmc-1991258, issue 7 register 0002h: tse master configuration bit type function default bit 15 r/w reserved[8] 1 bit 14 r/w wcimode 0 bit 13 r/w ilcv 0 bit 12 unused x bit 11 r/w reserved[7] 0 bit 10 r/w reserved[6] 1 bit 9 r/w reserved[5] 0 bit 8 r/w etse_mode 0 bit 7 unused x bit 6 unused x bit 5 r/w reserved[4] 0 bit 4 r/w reserved[3] 0 bit 3 r/w reserved[2] 0 bit 2 r/w reserved[1] 0 bit 1 r/w reserved[0] 0 bit 0 r/w itse_mode 0 this register configures the function of the 8b/ 10b encoders, decoder and the time switch blocks in the tse. itse_mode: the itse mode bit (itse_mode) control the function of itse blocks #1 through #16. if itse_mode is set to low, itse switching is controlled by the contents of the selected connection memory. if itse_mode is set high, the itse performs no switching function. reserved[8:0] the reserved[8:0] bits must be set to the indi cated default value for correct operation of the tse device. etse_mode the etse mode bit (etse_mode) control the function of etse blocks #1 through #16. if etse_mode is set to low, itse switching is controlled by the contents of the selected connection memory. if etse_mode is set high, the etse performs no switching function.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 document id: pmc-1991258, issue 7 ilcv the insert lcv bit (ilcv) controls the inse rtion of illegal 8b/10b characters in the datastream. if a line code violation is detected by an r8fa, and ilcv is logic 1, the tse will overwrite the character with the lcv with an illegal character (1110110100 or 0001001011). the insertion of an illegal character prevents lcvs due to disparity errors being masked by the t8de. if ilcv is logic 0, lcv characters are masked, and replaced with a legal data character, d12.3. masking lc vs prevents floating links from disrupting framing wcimode the write clear interrupt mode bit (wcimode) controls whether interrupt status bits are cleared on a read or a write to the corresponding register. if wcimode is logic 1, all interrupt status bits in interrupt status register are cleared when a logic high is written to the corresponding interrupt bit. otherwise, interrupt status bits are cleared on a register read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 document id: pmc-1991258, issue 7 register 0003h: tse master interrupt block identifier bit type function default bit 15 r/w reserved 0 bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r id_cstri x bit 4 r id_sswti x bit 3 r id_etsei x bit 2 r id_itsei x bit 1 r id_t8dei x bit 0 r id_r8fai x this register allows the source of an active interrupt to be identified down to the block function level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. id_r8fai the id_r8fai bit is high when an interrupt request is active from one of the 64 receive 8b/10b frame aligner (r8fa) bl ocks. the particular r8fa block which set the interrupt can be identified by reading the tse r8fa interrupt source registers. the id_r8fai bit is cleared when the interrupt is cleared. id_t8dei the id_t8dei bit is high when an interrupt request is active from one of the 64 transmit 8b/10b disparity encoder (t8de) blocks. the particular t8de block which set the interrupt can be identified by reading the tse t8de interrupt source registers. the id_t8dei bit is cleared when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:41 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 document id: pmc-1991258, issue 7 id_itsei the id_itsei bit is high when an interrupt request is active from one of the 16 ingress time switch element (itse) blocks. the particular itse block which set the interrupt can be identified by reading the tse itse interrupt so urce registers. the id_itsei bit is cleared when the interrupt is cleared. id_etsei the id_etsei bit is high when an interrupt request is active from one of the 16 egress time switch element (etse) blocks. the particular etse block which set the interrupt can be identified by reading the tse etse interrupt s ource registers. the id_etsei bit is cleared when the interrupt is cleared. id_sswti the id_sswti bit is high when an interrupt request is active from the space switch stage block. the id_sswti bit is cleared when the interrupt is cleared. id_cstri the id_cstri bit is high when an interrupt request is active from one of the cstr blocks and indicates a change in the lock status of a csu. the particular cstr block which set the interrupt can be identified by reading the tse cstr interrupt source registers. the id_cstri bit is cleared when the interrupt is cleared. reserved the reserved bit must be set to the indicated default value for proper function of the tse device.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 document id: pmc-1991258, issue 7 register 0004h: tse master r8fa interrupt source #1 bit type function default bit 15 r r8fai[16] x bit 14 r r8fai[15] x bit 13 r r8fai[14] x bit 12 r r8fai[13] x bit 11 r r8fai[12] x bit 10 r r8fai[11] x bit 9 r r8fai[10] x bit 8 r r8fai[9] x bit 7 r r8fai[8] x bit 6 r r8fai[7] x bit 5 r r8fai[6] x bit 4 r r8fai[5] x bit 3 r r8fai[4] x bit 2 r r8fai[3] x bit 1 r r8fai[2] x bit 0 r r8fai[1] x this register is used to indicate interrupts generated from the r8fa blocks #1 through #16. r8fai[16:1] the r8fa # x interrupt event indication (r8fai[x]) transitions to logic 1 when a hardware interrupt event is sourced from r8fa # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 document id: pmc-1991258, issue 7 register: 0005h: tse master r8fa interrupt source #2 bit type function default bit 15 r r8fai[32] x bit 14 r r8fai[31] x bit 13 r r8fai[30] x bit 12 r r8fai[29] x bit 11 r r8fai[28] x bit 10 r r8fai[27] x bit 9 r r8fai[26] x bit 8 r r8fai[25] x bit 7 r r8fai[24] x bit 6 r r8fai[23] x bit 5 r r8fai[22] x bit 4 r r8fai[21] x bit 3 r r8fai[20] x bit 2 r r8fai[19] x bit 1 r r8fai[18] x bit 0 r r8fai[17] x this register is used to indicate interrupts generated from the r8fa blocks #17 through #32. r8fai[32:17] the r8fa # x interrupt event indication (r8fai[x]) transitions to logic 1 when a hardware interrupt event is sourced from r8fa # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 document id: pmc-1991258, issue 7 register 0006h: tse master r8fa interrupt source #3 bit type function default bit 15 r r8fai[48] x bit 14 r r8fai[47] x bit 13 r r8fai[46] x bit 12 r r8fai[45] x bit 11 r r8fai[44] x bit 10 r r8fai[43] x bit 9 r r8fai[42] x bit 8 r r8fai[41] x bit 7 r r8fai[40] x bit 6 r r8fai[39] x bit 5 r r8fai[38] x bit 4 r r8fai[37] x bit 3 r r8fai[36] x bit 2 r r8fai[35] x bit 1 r r8fai[34] x bit 0 r r8fai[33] x this register is used to indicate interrupts generated from the r8fa blocks #33 through #48. r8fai[48:33] the r8fa # x interrupt event indication (r8fai[x]) transitions to logic 1 when a hardware interrupt event is sourced from r8fa # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 document id: pmc-1991258, issue 7 register 0007h: tse master r8fa interrupt source #4 bit type function default bit 15 r r8fai[64] x bit 14 r r8fai[63] x bit 13 r r8fai[62] x bit 12 r r8fai[61] x bit 11 r r8fai[60] x bit 10 r r8fai[59] x bit 9 r r8fai[58] x bit 8 r r8fai[57] x bit 7 r r8fai[56] x bit 6 r r8fai[55] x bit 5 r r8fai[54] x bit 4 r r8fai[53] x bit 3 r r8fai[52] x bit 2 r r8fai[51] x bit 1 r r8fai[50] x bit 0 r r8fai[49] x this register is used to indicate interrupts generated from the r8fa blocks #49 through #64. r8fai[64:49] the r8fa # x interrupt event indication (r8fai[x]) transitions to logic 1 when a hardware interrupt event is sourced from r8fa # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 document id: pmc-1991258, issue 7 register 0008h: tse master t8de interrupt source #1 bit type function default bit 15 r t8dei[16] x bit 14 r t8dei[15] x bit 13 r t8dei[14] x bit 12 r t8dei[13] x bit 11 r t8dei[12] x bit 10 r t8dei[11] x bit 9 r t8dei[10] x bit 8 r t8dei[9] x bit 7 r t8dei[8] x bit 6 r t8dei[7] x bit 5 r t8dei[6] x bit 4 r t8dei[5] x bit 3 r t8dei[4] x bit 2 r t8dei[3] x bit 1 r t8dei[2] x bit 0 r t8dei[1] x this register is used to indicate interrupts generated from the t8de blocks #1 through #16. t8dei[16:1] the t8de # x interrupt event indication (t8dei[x]) transitions to logic 1 when a hardware interrupt event is sourced from t8de # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 document id: pmc-1991258, issue 7 register 0009h: tse master t8de interrupt source #2 bit type function default bit 15 r t8dei[32] x bit 14 r t8dei[31] x bit 13 r t8dei[30] x bit 12 r t8dei[29] x bit 11 r t8dei[28] x bit 10 r t8dei[27] x bit 9 r t8dei[26] x bit 8 r t8dei[25] x bit 7 r t8dei[24] x bit 6 r t8dei[23] x bit 5 r t8dei[22] x bit 4 r t8dei[21] x bit 3 r t8dei[20] x bit 2 r t8dei[19] x bit 1 r t8dei[18] x bit 0 r t8dei[17] x this register is used to indicate interrupts generated from the t8de blocks #17 through #32. t8dei[32:17] the t8de # x interrupt event indication (t8dei[x]) transitions to logic 1 when a hardware interrupt event is sourced from t8de # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 document id: pmc-1991258, issue 7 register 000ah: tse master t8de interrupt source #3 bit type function default bit 15 r t8dei[48] x bit 14 r t8dei[47] x bit 13 r t8dei[46] x bit 12 r t8dei[45] x bit 11 r t8dei[44] x bit 10 r t8dei[43] x bit 9 r t8dei[42] x bit 8 r t8dei[41] x bit 7 r t8dei[40] x bit 6 r t8dei[39] x bit 5 r t8dei[38] x bit 4 r t8dei[37] x bit 3 r t8dei[36] x bit 2 r t8dei[35] x bit 1 r t8dei[34] x bit 0 r t8dei[33] x this register is used to indicate interrupts generated from the t8de blocks #33 through #48. t8dei[48:33] the t8de # x interrupt event indication (t8dei[x]) transitions to logic 1 when a hardware interrupt event is sourced from t8de # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 document id: pmc-1991258, issue 7 register 000bh: tse master t8de interrupt source #4 bit type function default bit 15 r t8dei[64] x bit 14 r t8dei[63] x bit 13 r t8dei[62] x bit 12 r t8dei[61] x bit 11 r t8dei[60] x bit 10 r t8dei[59] x bit 9 r t8dei[58] x bit 8 r t8dei[57] x bit 7 r t8dei[56] x bit 6 r t8dei[55] x bit 5 r t8dei[54] x bit 4 r t8dei[53] x bit 3 r t8dei[52] x bit 2 r t8dei[51] x bit 1 r t8dei[50] x bit 0 r t8dei[49] x this register is used to indicate interrupts generated from the t8de blocks #49 through #64. t8dei[64:49] the t8de # x interrupt event indication (t8dei[x]) transitions to logic 1 when a hardware interrupt event is sourced from t8de # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 document id: pmc-1991258, issue 7 register 000ch: tse master itse interrupt source bit type function default bit 15 r itsei[16] x bit 14 r itsei[15] x bit 13 r itsei[14] x bit 12 r itsei[13] x bit 11 r itsei[12] x bit 10 r itsei[11] x bit 9 r itsei[10] x bit 8 r itsei[9] x bit 7 r itsei[8] x bit 6 r itsei[7] x bit 5 r itsei[6] x bit 4 r itsei[5] x bit 3 r itsei[4] x bit 2 r itsei[3] x bit 1 r itsei[2] x bit 0 r itsei[1] x this register is used to indicate interrupts generated from the itse blocks #1 through #16. itsei[16:1] the itse # x interrupt event indication (itsei[x]) transitions to logic 1 when a hardware interrupt event is sourced from itse # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 document id: pmc-1991258, issue 7 register 000dh: tse master etse interrupt source bit type function default bit 15 r etsei[16] x bit 14 r etsei[15] x bit 13 r etsei[14] x bit 12 r etsei[13] x bit 11 r etsei[12] x bit 10 r etsei[11] x bit 9 r etsei[10] x bit 8 r etsei[9] x bit 7 r etsei[8] x bit 6 r etsei[7] x bit 5 r etsei[6] x bit 4 r etsei[5] x bit 3 r etsei[4] x bit 2 r etsei[3] x bit 1 r etsei[2] x bit 0 r etsei[1] x this register is used to indicate interrupts generated from the etse blocks #1 through #16. etsei[16:1] the etse # x interrupt event indication (etsei[x]) transitions to logic 1 when a hardware interrupt event is sourced from etse # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 document id: pmc-1991258, issue 7 register 000eh: tse master cstr interrupt source bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r cstri[4] x bit 2 r cstri[3] x bit 1 r cstri[2] x bit 0 r cstri[1] x this register is used to indicate interrupts generated from the cstr blocks #1 through #4. cstri[4:1] the cstr # x interrupt event indication (cstri[x]) transitions to logic 1 when a hardware interrupt event is sourced from cstr # x block. this bit is cleared to logic 0 when the interrupt is cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 document id: pmc-1991258, issue 7 register 000fh: tse master user defined bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r/w free[7] 0 bit 6 r/w free[6] 0 bit 5 r/w free[5] 0 bit 4 r/w free[4] 0 bit 3 r/w free[3] 0 bit 2 r/w free[2] 0 bit 1 r/w free[1] 0 bit 0 r/w free[0] 0 free[7:0] the free[7:0] register bits do not perform an y function. they are free for user defined read/write operations.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 document id: pmc-1991258, issue 7 register 0010h: tse master jtag id high bit type function default bit 15 r id[3] 0 bit 14 r id[2] 0 bit 13 r id[1] 0 bit 12 r id[0] 1 bit 11 r devid[15] 0 bit 10 r devid[14] 1 bit 9 r devid[13] 0 bit 8 r devid[12] 1 bit 7 r devid[11] 0 bit 6 r devid[10] 0 bit 5 r devid[9] 1 bit 4 r devid[8] 1 bit 3 r devid[7] 0 bit 2 r devid[6] 1 bit 1 r devid[5] 1 bit 0 r devid[4] 1 the tse master jtag id registers hold the jtag identification code for the device. the device revision number and device id are available through these registers. devid[15:0] the devid bits can be read to distinguish the tse from other devices. devid returns 5372h when read. devid[3:0] bits are found in register 0011h: tse master jtag id low. id[3:0] the id bits can be read to provide a binary tse revision number.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 document id: pmc-1991258, issue 7 register 0011h: tse master jtag id low bit type function default bit 15 r devid[3] 0 bit 14 r devid[2] 0 bit 13 r devid[1] 1 bit 12 r devid[0] 0 bit 11 r mid[10] 0 bit 10 r mid[9] 0 bit 9 r mid[8] 0 bit 8 r mid[7] 0 bit 7 r mid[6] 1 bit 6 r mid[5] 1 bit 5 r mid[4] 0 bit 4 r mid[3] 0 bit 3 r mid[2] 1 bit 2 r mid[1] 1 bit 1 r mid[0] 0 bit 0 r jid 1 jid the jid bit is bit 0 in the jtag identification code. mid[10:0] the mid bits provide the manufacturer identify field in the jtag identification code. mid returns 066h when read. devid[15:0] the devid bits can be read to distinguish the tse from other devices. devid returns 5372h when read. devid[15:4] bits are found in register 0010h: tse master jtag id high.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 document id: pmc-1991258, issue 7 register 0020h, 00024h, 0028h, 002ch: cstr #1 ? #4 control bit type function default bit 15 r/w reserved[11] 0 bit 14 r/w reserved[10] 0 bit 13 r/w reserved[9] 0 bit 12 r/w reserved[8] 0 bit 11 r/w reserved[7] 0 bit 10 r/w reserved[6] 1 bit 9 r/w reserved[5] 0 bit 8 r/w reserved[4] 0 bit 7 r/w reserved[3] 0 bit 6 r/w reserved[2] 0 bit 5 r/w reserved[1] 0 bit 4 r/w csu_enb 0 bit 3 r/w csu_rstb 1 bit 2 unused x bit 1 unused x bit 0 r/w reserved[0] 1 this register provides reset control and enable control for cstr blocks #1 through #4 reserved[11:0] the reserved[11:0] bits must be set to the indicated default value for correct operation of the tse. csu_rstb the csu_rstb signal is a software reset signal that forces the csu into reset. the csu is reset when the csu_rstb is logic 0. the csu is also reset by the tse master analog reset signal. when the csu is reset, the reset signal should be held for at least 100us. csu_enb the csu enable control signal (csu_enb) bit forces the csu into low power configuration. the csu is disabled when csu_enb is logic 1. the csu is enabled when csu_enb is logic 0.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 document id: pmc-1991258, issue 7 register 0021h, 00025h, 0029h, 002dh: cstr #1 ? #4 interrupt enable and csu lock status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r lockv x bit 0 r/w locke 0 this register configures the operation of cstr blocks #1 through #4. locke the csu lock interrupt enable bit (locke) controls the contribution of csu lock state interrupts by the cstr to the device interrupt intb. when locke is high, intb is asserted low when the csu lock state changes. interrupts due to csu lock state are masked when locke is set low. lockv the csu lock status bit (lockv) indicates whether the clock synthesis unit has successfully locked with the system clock. lockv is set low when the csu has not successfully locked with the reference clock. lockv is set high if when the csu has locked with the reference clock.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 document id: pmc-1991258, issue 7 register 0022h, 00026h, 002ah, 002eh: cstr #1 ? #4 interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r locki x this register reports the interrupt status of cstr blocks #1 through #4. locki the csu lock interrupt status bit (locki) reports and acknowledges changes in the csu lock state. locki is set high when the csu achieves lock with the reference clock or loses its lock to the reference clock. locki is cleared on a read to this register when wcimode is logic 0. locki is cleared on a write of logic 1 to locki when wcimode is logic 1. intb is asserted low when both locke and locki are high. if locke is asserted, locki must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 document id: pmc-1991258, issue 7 register 0040h: sswt rj0fp delay bit type function default bit 15 unused x bit 14 unused x bit 13 r/w rj0dly[13] 0 bit 12 r/w rj0dly[12] 0 bit 11 r/w rj0dly[11] 0 bit 10 r/w rj0dly[10] 0 bit 9 r/w rj0dly[9] 0 bit 8 r/w rj0dly[8] 0 bit 7 r/w rj0dly[7] 0 bit 6 r/w rj0dly[6] 0 bit 5 r/w rj0dly[5] 0 bit 4 r/w rj0dly[4] 0 bit 3 r/w rj0dly[3] 0 bit 2 r/w rj0dly[2] 0 bit 1 r/w rj0dly[1] 0 bit 0 r/w rj0dly[0] 0 this register controls the delay from the rj0fp input signal to the time when the tse may safely process the j0 characters delivered by the receive data links (rp [64:1]/rn[64:1]). rj0dly[13:0] the receive transport frame delay bits (rj0dly[13:0]) controls the delay from the rj0fp pulse clock cycle, in sysclk cycles, inserted by the tse before processing the j0 characters delivered by the receive serial data links. rj0dly is set such that after the specified delay, all active receive links would have delivered the j0 character to the receive fifo in the r8fa. rj0dly has valid range between 1 to 9719 inclusive. the relationships of rj0fp, rj0dly[13:0] and the system configur ation are described in figure 20, figure 21, and figure 22.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 document id: pmc-1991258, issue 7 register 0041h: sswt indirect control address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 r/w pgsel 0 bit 12 unused x bit 11 r/w tslot[3] 0 bit 10 r/w tslot[2] 0 bit 9 r/w tslot[1] 0 bit 8 r/w tslot[0] 1 bit 7 unused x bit 6 unused x bit 5 r/w doutsel[5] 0 bit 4 r/w doutsel[4] 0 bit 3 r/w doutsel[3] 0 bit 2 r/w doutsel[2] 0 bit 1 r/w doutsel[1] 0 bit 0 r/w doutsel[0] 0 this register provides the sswt outgoing stream number, time slot number, and control page number used to access the space switch control blocks of the sswt outgoing data streams. writing to this register triggers an indirect register access and transfers the contents of the indirect mux control data register to an internal holding register. doutsel[5:0] doutsel[5:0] selects the space switch control bl ock in an indirect mux control access. the correspondence between doutsel, sswt output port and the connected etse input port are as follows. doutsel[5:0] etse block # etse input port # transmit serial link (tp[ x ]/tn[ x ]) 0 1 1 1 1 1 2 2 2 1 3 3 3 1 4 4 . . . . 4n n+1 1 4n+1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 document id: pmc-1991258, issue 7 4n+1 n+1 2 4n+2 4n+2 n+1 3 4n+3 4n+3 n+1 4 4n+4 . . . . 63 16 4 64 tslot[3:0] the indirect time-slot number bits (tslot[3:0]) indicate the time-slot to be configured or interrogated in the indirect access. for the data incoming to the sswt, time-slots 1 to 12 are valid. indices 0 and 13 to 15 are invalid. an invalid index will result in immediate deassertion of the busy bit and undefined results in the dinsel register. the following table shows valid tslot values. table 13 control word index tslot[3:0] sts-1/stm-0 time slot # 0000 invalid time slot 0001-1100 time slot #1 to time slot #12 1101-1111 invalid time slot pgsel the pgsel specifies the control page of the space switch control block in an indirect mux control access. when pgsel is logic 0, cont rol page 0 is selected. when pgsel is 1, control page 1 is selected. rwb the indirect access control bit (rwb) selects between a configure (write) or interrogate (read) access to the space switch control blocks. the address to the control registers is constructed from the doutsel[5:0] and tslot[3:0] fields. writing a logic zero to rwb triggers an indirect write operation. data to be written is taken from the dinsel[6:0] data register. writing a logic one to rwb triggers an indirect read operation. addressing of the switch control block is the same as in an indirect write operation. the data read can be found in dinsel[6:0] after the busy bit has cleared.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 document id: pmc-1991258, issue 7 busy the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when this register is written to trigger an indirect access, and will stay high until the access is complete, at which point busy will be cleared (set low). this register should be polled to determine when data from an indirect read operation is available in the indirect data register or to determine when a new indirect write operation may commence. any indirect operation that is initiated while busy is still high will be corrupted. the busy bit shows a default of ?x?. this does not require the bit to be cleared after a reset since the bit resets to 0 a few clock cycles after a reset. the bit is undefined for a short period (a few clock cycles) after a reset but the user will never read ?1? as the bit would clear before the bit is queried.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 document id: pmc-1991258, issue 7 register 0042h: sswt indirect control data bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w dinsel[5] 0 bit 4 r/w dinsel[4] 0 bit 3 r/w dinsel[3] 0 bit 2 r/w dinsel[2] 0 bit 1 r/w dinsel[1] 0 bit 0 r/w dinsel[0] 0 this register contains data to be written into the control word in an indirect write access, or the data read from the control word in an indirect read access for the sswt block. dinsel[5:0] the dinsel[5:0] specifies one control word within a page of a space switch control block. in an indirect write operation, the control words must be set up in this register before triggering the indirect write. when read back , dinsel[5:0] reflects the value written until the completion of a subsequent indirect channel read operation. the control word directs which of the 64 input data words is selected for the output timeslot. the correspondence between dinsel, sswt input ports, and the attached itse output ports is shown in the following table. dinsel[5:0] itse block # itse output port # receive serial link (rp[ x ]/rn[ x ]) 0 1 1 1 1 1 2 2 2 1 3 3 3 1 4 4
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 document id: pmc-1991258, issue 7 dinsel[5:0] itse block # itse output port # receive serial link (rp[ x ]/rn[ x ]) . . . . 4n n+1 1 4n+1 4n+1 n+1 2 4n+2 4n+2 n+1 3 4n+3 4n+3 n+1 4 4n+4 . . . . 63 16 4 64
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 document id: pmc-1991258, issue 7 register 0043h: sswt interrupt enable bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r sactive x bit 1 r/w spsel 0 bit 0 r/w scoape 0 this register provides interrupt enable control for the sswt block scoape the change of active page interrupt enable bit (scoape) masks the contribution of the change of active page event indication bit (scoapi) in the sswt block to intb. when scoape is high, intb is asserted low when scoapi is high. intb is not affected by the value of scoapi when scoape is low. spsel the page select (spsel) bit is used in the selection of the current active page for the mux control blocks. this bit is logically xored with the value of cmp to determine the next control page selection. sactive the active page indication (sactive) bit indicates which control page is currently active in the muxing blocks. when this bit is logic 0 then page 0 is active. when this bit is logic 1 then page 1 is active.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 document id: pmc-1991258, issue 7 register 0044h: sswt interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r scoapi x this register provides the interrupt status of the sswt block. scoapi the change of active page interrupt (scoapi) reports a change in the active page event for the sswt. scoapi is set high when a change of active page has occurred since the last clear for the register. scoapi is cleared on a read to this register when wcimode is logic 0. scoapi is cleared on a write of logic 1 to scoapi when wcimode is logic 1. intb is asserted low when both scoape and scoapi ar e high. if scoape is asserted, scoapi must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 document id: pmc-1991258, issue 7 register 0047h: sswt tj0fp delay bit type function default bit 15 unused x bit 14 unused x bit 13 r/w tj0dly[13] 0 bit 12 r/w tj0dly[12] 0 bit 11 r/w tj0dly[11] 0 bit 10 r/w tj0dly[10] 0 bit 9 r/w tj0dly[9] 0 bit 8 r/w tj0dly[8] 0 bit 7 r/w tj0dly[7] 0 bit 6 r/w tj0dly[6] 0 bit 5 r/w tj0dly[5] 1 bit 4 r/w tj0dly[4] 0 bit 3 r/w tj0dly[3] 0 bit 2 r/w tj0dly[2] 1 bit 1 r/w tj0dly[1] 1 bit 0 r/w tj0dly[0] 0 this register controls the delay from the rj0fp input signal to the assertion of the tj0fp signal, meant to signify the transmission of j0s from all transmit ports tp[64:1]/tn[64:1]. tj0dly[13:0] the transmit transport frame delay bits (tj0dl y[13:0]) controls the delay from the rj0fp pulse clock cycle, in sysclk cycles, inserted by the tse before asserting the tj0fp signal. the delay between rj0fp and the assertion of tj0fp will be tj0dly + 2 cycles. it is suggested that tj0dly is set so tj0fp assertion signifies the departure of all j0s from the transmit ports. if tj0fp is used for that purpose, tj0dly should be set to rj0dly+ 47. figure 21 illustrates the relationship between rj0fp, rj0dly and tj0dly.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 document id: pmc-1991258, issue 7 register 0n80h, 0n88h, 0n90h, 0n98h: port set #1 - #16 r8fa #1 - #4 control and status bit type function default bit 15 r/w reserved 0 bit 14 r/w j0mask 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r/w rxinv 0 bit 8 r/w ofaais 0 bit 7 r/w fuoe 0 bit 6 r/w lcve 0 bit 5 r/w ofae 0 bit 4 r/w ocae 0 bit 3 r ofav x bit 2 r ocav x bit 1 r/w fofa 0 bit 0 r/w foca 0 this set of registers provides control and reports the status of r8fa blocks #1 through #64. registers 0n80h, 0n88h, 0n90h and 0n98h are associated with r8fa blocks #1 to #4 respectively, in port set n+1. foca the force out-of-character-alignment bit (foca) control the operation of the character alignment block in the corresponding r8fa block. a 0-1 transition on this bit forces the character alignment block to the out-of-character-alignment state where it will search for the transport frame alignment character (k28.5). before another force operation can be performed, foca must first be set to logic 0. fofa the force out-of-frame-alignment bit (fofa) controls the operation of the frame alignment block in the corresponding r8fa block. a 0-1 transition on this bit forces the frame alignment block to the out-of-frame-alignment state where it will search for the transport frame alignment character (k28.5). before another force operation can be performed, fofa must first be set to logic 0.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 document id: pmc-1991258, issue 7 ocav the out-of-character-alignment status bit (ocav) reports the state of the character alignment block in the corresponding r8fa block. ocav is set high when the character alignment block is in the out-of-character-alignment state. ocav is set low when the character alignment block is in the in-character-alignment state. ofav the out-of-frame-alignment status bit (ofav) reports the state of the frame alignment block in the corresponding r8fa block. ofav is set high when the frame alignment block is in the out-of-frame-alignment state. ofav is set low when the frame alignment block is in the in- frame-alignment state. ocae the out of character alignment interrupt enable bit (ocae) masks the contribution of the change of character alignment event indicati on bit (ocai) in the corresponding r8fa block to intb. when ocae is high, intb is asserted low when ocai is high. intb is not affected by the value of ocai when ocae is low. ofae the out of frame alignment interrupt enable bi t (ofae) masks the contribution of the change of frame alignment event indication bit (ofai) in the corresponding r8fa block to intb. when ofae is high, intb is asserted low when ofai is high. intb is not affected by the value of ofai when ofae is low. lcve the line code violation interrupt enable bit (lcve) masks the contribution of the line code violation event indication bit (lcvi) in the corresponding r8fa block to intb. when lcve is high, intb is asserted low when lcvi is high. intb is not affected by the value of lcvi when lcve is low. fuoe the fifo underrun/overrun status interrupt enab le bit (fuoe) masks the contribution of the fifo underrun/overrun event indication bit (fuoi) in the corresponding r8fa block to intb. when fuoe is high, intb is asserted low when fuoi is high. intb is not affected by the value of fuoi when fuoe is low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 document id: pmc-1991258, issue 7 ofaais the out of frame alignment alarm indication signal (ofaais) is set high to force insertion of the high order path ais, k28.4- character in the data stream if the corresponding r8fa block is in the out of frame alignment state. rxinv the receive data invert bit (rxinv) controls the active polarity of the incoming data stream. when rxinv is set high, the data is complemented before any processing by the corresponding r8fa. when rxinv is set low, data is not complemented before r8fa processing. j0mask the j0 masking bit (j0mask) controls the overwriting of k28.5 characters in the datastream. when j0mask is set high, k28.5 characters are replaced by either d12.3-: ?001101 0011? or d12.3+: ?001101 1100? characters. this mode of operation prevents spurious k28.5 characters resulting from floating links or bit errors from passing through the tse and disrupting framing in downstream devices. when j0mask is set low, k28.5 characters on the datastream are not replaced. if j0/z0 switching is enabled using the ij0rorder and ej0rordr bits, then j0 masking is recomm ended to prevent reordering of the k28.5 character and disruption of downstream framers. reserved the reserved bit must be set to the indicated default value for correct operation of the tse.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 document id: pmc-1991258, issue 7 register 0n81h, 0n89h, 0n91h, 0n99h: port set #1 - #16 r8fa #1 - #4 interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r fuoi x bit 6 r lcvi x bit 5 r ofai x bit 4 r ocai x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x these registers report interrupt status due to change of character alignment events and detection of line code violations for the r8fa bloc ks #1 - #64. registers 0n81h, 0n89h, 0n91h and 0n99h are associated with r8fa blocks #1 - #4 respectively, in port set n+1. ocai the out-of-character-alignment interrupt status bit (ocai) reports and acknowledges change of character alignment state events for the r8fa block. ocai is set high when the character alignment block changes state to the out-of-character-alignment state or to the in-character- alignment state since the last clear for the register. ocai is cleared on a read to this register when wcimode is logic 0. ocai is cleared on a write of logic 1 to ocai when wcimode is logic 1. intb is asserted low wh en both ocae and ocai are high. if ocae is asserted, ocai must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 document id: pmc-1991258, issue 7 ofai the out-of-frame-alignment interrupt status bit (ofai) reports and acknowledges change of frame alignment state events for the r8fa block. ofai is set high when the frame alignment block changes state to the out-of-frame-alignmen t state or to the in-frame-alignment state. ofai is cleared on a read to this register when wcimode is logic 0. ofai is cleared on a write of logic 1 to ofai when wcimode is logic 1. intb is asserted low when both ofae and ofai are high. if ofae is asserted, ofai must be cleared before intb will be reasserted. lcvi the line code violation event interrupt status bit (lcvi) reports and acknowledges line code violation events for the r8fa block. lcvi is set high when the character alignment block detects a line code violation in the incoming data stream. lcvi is cleared on a read to this register when wcimode is logic 0. lcvi is cleared on a write of logic 1 to lcvi when wcimode is logic 1. intb is asserted low when both lcve and lcvi are high. if lcve is asserted, lcvi must be cleared before intb will be reasserted. note that an uninterrupted stream of line code violations will produce a single lcvi event as it is the transition from not detecting and lcv to detect ing an lcv that causes lcvi to be set. fuoi the fifo underrun/overrun event interrupt status bit (fuoi) reports and acknowledges the fifo underrun/overrun events for the r8fa block. fuoi is set high when r8fa detects that the fifo read and write pointers are within one slot of each other. fuoi is cleared on a read to this register when wcimode is logic 0. fuoi is cleared on a write of logic 1 to fuoi when wcimode is logic 1. intb is asserted low when both fuoe and fuoi are high. if fuoe is asserted, fuoi must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 document id: pmc-1991258, issue 7 register 0n82h, 0n8ah, 0n92h, 0n9ah: port set #1 - #16 r8fa #1 - #4 line code violation count bit type function default bit 15 r lcv[15] x bit 14 r lcv[14] x bit 13 r lcv[13] x bit 12 r lcv[12] x bit 11 r lcv[11] x bit 10 r lcv[10] x bit 9 r lcv[9] x bit 8 r lcv[8] x bit 7 r lcv[7] x bit 6 r lcv[6] x bit 5 r lcv[5] x bit 4 r lcv[4] x bit 3 r lcv[3] x bit 2 r lcv[2] x bit 1 r lcv[1] x bit 0 r lcv[0] x these registers report the number of line code violations in the previous accumulation period for the r8fa block #1 through #64. lcv[15:0] the lcv[15:0] bits reports the number of line code violations that have been detected since the last time the lcv registers were polled. the lcv registers are polled by writing to the tip register or by writing to this register. within 10 us of either event, the internally accumulated error count is transferred to the lcv registers and the internal error counter is simultaneously reset to begin a new cycle of error accumulation. when the diagnose line code violation bit (dlcv) in an upstream device is set to logic 1 in order to create line code violations, it is possible to saturate this register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 document id: pmc-1991258, issue 7 register 0n83h, 0n8bh, 0n93h, 0n9bh: port set #1 - #16 rxlv and dru #1 - #4 control bit type function default bit 15 r/w reserved[7] 1 bit 14 r/w reserved[6] 1 bit 13 r/w dru_enb 0 bit 12 r/w rx_enb 0 bit 11 r/w reserved[5] 0 bit 10 r/w a_rstb 1 bit 9 r/w reserved[4] 0 bit 8 r/w reserved[3] 0 bit 7 r/w reserved[2] 0 bit 6 r/w reserved[1] 0 bit 5 r/w dru_ctrl[3] 0 bit 4 r/w dru_ctrl[2] 0 bit 3 r/w dru_ctrl[1] 0 bit 2 r/w dru_ctrl[0] 0 bit 1 r/w reserved[0] 0 bit 0 unused x these registers drive the control signals for rxlv and dru blocks #1 through #64. reserved[4:0] the reserved[4:0] bits must be set to the indi cated default value for correct operation of the tse. dru_ctrl[3:0] the dru_ctrl[3:0] bits control the dru ctrl[3:0] inputs. the dru_ctrl[3:0] bus is reset to 0000, but needs to be set to 1101 following a reset for correct operation of the tse. a_rstb the a_rstb bit is a soft-reset for the data recovery unit analog block. setting a_rstb to logic 0 will reset the block.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 document id: pmc-1991258, issue 7 reserved[5] the reserved[5] bit is set to logic 0 on reset, but needs to be set to logic 1 following reset for correct operation of the tse. rx_enb the rxlv enable bit (rx_enb) bit controls the operation of rxlv block #x. setting rx_enb to logic 0 enables the block. setting rx_enb to logic 1 disables the block. dru_enb the dru enable bit (dru_enb) bit controls th e operation of data recovery unit analog block #x. setting dru_enb to logic 0 enables the block. setting dru_enb to logic 1 disables the block. reserved[7:6] the reserved[7:6] bits must be set to the indi cated default value for correct operation of the tse.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 document id: pmc-1991258, issue 7 register 0na0h: port set #1 - #16, itse indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 r/w page 0 bit 9 unused x bit 8 unused x bit 7 r/w tsout[3] 0 bit 6 r/w tsout[2] 0 bit 5 r/w tsout[1] 0 bit 4 r/w tsout[0] 0 bit 3 unused x bit 2 unused x bit 1 r/w doutsel[1] 0 bit 0 r/w doutsel[0] 0 these registers provide the itse output port identifier, the time-slot number and the control page select used to access the control pages in the itse blocks #1 through #16. writing to this register triggers an indirect register access. doutsel[1:0] the data output select (doutsel[1:0]) bits se lect which itse output port configuration is accessed by the current indirect transfer. data from timeslot tsin[3:0] of incoming datastream dinsel[1:0] is transferred to timeslot tsout[3:0] to the output port selected by doutsel[1:0]. itse block #n+1 (n from 0 ? 15) doutsel[1:0] itse output port # receive serial link rp[ x ]/rn[ x ] 00 1 4n+1 01 2 4n+2 10 3 4n+3 11 4 4n+4
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 document id: pmc-1991258, issue 7 tsout[3:0] the indirect sts-1/stm-0 output time slot (tsout[3:0]) select bits for the itse block indicate the sts-1/stm-0 output time slot within the datastream selected by doutsel[1:0] that is accessed in the current indirect access. valid time-slot values are ?b0001 to ?b1100. tsout[3:0] sts-1/stm-0 time slot # 0000 invalid time slot 0001-1100 time slot #1 to time slot #12 1101-1111 invalid time slot page the connection memory page select bit (page) selects the connection memory page to be accessed in the current indirect access. when page is set high, page 1 is selected. when page is set low, page 0 is selected. rwb the indirect access control bit (rwb) selects between a configure (write) or interrogate (read) access to the control pages for the itse block. writing a logic 0 to rwb triggers an indirect write operation. data to be written is taken for the itse indirect data register. writing a logic 1 to rwb triggers an indirect read operation. the data read from the control pages is stored in the itse indirect data register after the busy bit has cleared. busy the indirect access status bit (busy) reports the progress of an indirect access for the itse block. busy is set to logic 1 when this register is written, triggering an access. it remains logic 1 until the access is complete at which time it is set to logic 0. these registers should be polled to determine when new data is available in the itse indirect data register or when another write access can be initiated. the busy bit shows a default of ?x?. this does not require the bit to be cleared after a reset since the bit resets to 0 a few clock cycles after a reset. the bit is undefined for a short period (a few clock cycles) after a reset but the user will never read ?1? as the bit would clear before the bit is queried.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 document id: pmc-1991258, issue 7 register 0na1h: port set #1 - #16 itse indirect data bit type function default bit 15 unused x bit 14 unused x bit 13 r/w reserved[7] 0 bit 12 r/w reserved[6] 0 bit 11 r/w reserved[5] 0 bit 10 r/w reserved[4] 0 bit 9 r/w reserved[3] 0 bit 8 r/w reserved[2] 0 bit 7 r/w tsin[3] 0 bit 6 r/w tsin[2] 0 bit 5 r/w tsin[1] 0 bit 4 r/w tsin[0] 0 bit 3 r/w reserved[1] 0 bit 2 r/w reserved[0] 0 bit 1 r/w dinsel[1] 0 bit 0 r/w dinsel[0] 0 these registers contain the data read from the control pages after an indirect read operation or the to be data written to the control pages in an indirect write operation for the itse block. dinsel[1:0] the data input select (dinsel[1:0]) bits report the itse input port identifier read after an indirect read operation has completed for the itse block. the input port identifier to be written to the control pages must be set in dinsel[1:0] before triggering a write. dinsel[1:0] reflects the last value read or written until the completion of a subsequent indirect read operation. reserved[7:0] the reserved[7:0] bits must be set as shown for correct operation of the tse.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 document id: pmc-1991258, issue 7 tsin[3:0] the sts-1/stm-0 input time slot (tsin[3:0]) bits report the time-slot number read after an indirect read operation has completed. the time-slot number to be written to the control pages must be set up in this register before triggering a write. tsin [3:0] reflects the last value read or written until the completion of a subsequent indirect read operation. time slots b?0001 to ?b1100are valid. writing an invalid time-slot value results in undefined behavior. tsin[3:0] sts-1/stm-0 time slot # 0000 invalid time slot 0001-1100 time slot #1 to time slot #12 1101-1111 invalid time slot
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 document id: pmc-1991258, issue 7 register 0na2h: port set #1 - #16 itse configuration bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r iactive x bit 2 r/w ipsel 0 bit 1 r/w ij0rordr 0 bit 0 r/w icoape 0 these registers provide page selection, active page indication, j0 reordering mode, and interrupt masking control for itse blocks #1 through #16. icoape the change of active page interrupt enable bit (icoape) masks the contribution of the change of active page event indication bit (icoapi) in the isti block to intb. when icoape is high, intb is asserted low when icoapi is high. intb is not affected by the value of icoapi when icoape is low. ij0rordr the incoming j0 reorder bit controls the reordering of j0/z0 bytes in the four sts-12 datastreams through the n th itse block. time slot interchange of the j0/z0 bytes in the n th itse is suspended when j0/z0 reordering is di sabled. when ij0rordr is set low, the j0/z0 bytes are not reordered. when ij0rordr is set high, j0/z0 byte reordering is enabled. if j0 reordering is enabled, j0 masking should also be enabled in the upstream r8fas to prevent k28.5 characters from being switched to a position other than j0. j0 masking is done using the j0mask bit in register 0n80h, 0n88h, 0n 90h, and 0n98h.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 document id: pmc-1991258, issue 7 ipsel the page select (ipsel) bit is used in the selection of the current active. this bit is logically xored with the value of the cmp signal to dete rmine which control page is currently active. if the xor result is logic 1, control page 1 is selected. otherwise, control page 0 is selected. iactive the active page indication (iactive) bit indicates which control page is currently active in the associated muxing blocks. when this bit is logic 0 then page 0 is active. when this bit is logic 1 then page 1 is active.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 document id: pmc-1991258, issue 7 register 0na3h: port set #1 - #16, itse interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r icoapi x these registers provide the interrupt status of itse blocks #1 through #16. icoapi the change of active page interrupt (icoapi) reports a change in the active page event for the itse. icoapi is set high when a change of active page has occurred since the last clear for the register. icoapi is cleared on a read to this register when wcimode is logic 0. icoapi is cleared on a write of logic 1 to icoapi when wcimode is logic 1. intb is asserted low when both icoape and icoapi are high. if icoape is asserted, icoapi must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 document id: pmc-1991258, issue 7 register 0na8h: port set #1 - #16, etse indirect address bit type function default bit 15 r busy 0 bit 14 r/w rwb 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 r/w page 0 bit 9 unused x bit 8 unused x bit 7 r/w tsout[3] 0 bit 6 r/w tsout[2] 0 bit 5 r/w tsout[1] 0 bit 4 r/w tsout[0] 0 bit 3 unused x bit 2 unused x bit 1 r/w doutsel[1] 0 bit 0 r/w doutsel[0] 0 these registers provide the etse output port identifier, the time-slot number and the control page select used to access the control pages for etse blocks #1 through #16. writing to this register triggers an indirect register access. doutsel[1:0] the data output select (doutsel[1:0]) bits select which etse output port configuration is accessed by the current indirect transfer. data from timeslot tsin[3:0] of incoming data of incoming datastream dinsel[1:0] is transferre d to timeslot tsout[3:0] to the output port selected by doutsel[1:0]. etse block #n+1 (n from 0 ? 15) doutsel[1:0] etse output port # transmit serial link tp[x]/tn[x] 00 1 4n+1 01 2 4n+2 10 3 4n+3 11 4 4n+4
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 document id: pmc-1991258, issue 7 tsout[3:0] the indirect sts-1/stm-0 output time slot (tsout[3:0]) select bits for the etse block indicate the sts-1/stm-0 output time slot within the datastream selected by doutsel[1:0] that is accessed in the current indirect access. valid time-slot values are ?b0001 to ?b1100. tsout[3:0] sts-1/stm-0 time slot # 0000 invalid time slot 0001-1100 time slot #1 to time slot #12 1101-1111 invalid time slot page the connection memory page select bit (page) selects the connection memory page to be accessed in the current indirect access. when page is set high, page 1 is selected. when page is set low, page 0 is selected. rwb the indirect access control bit (rwb) selects between a configure (write) or interrogate (read) access to the control pages for the itse block. writing a logic 0 to rwb triggers an indirect write operation. data to be written is taken for the itse indirect data register. writing a logic 1 to rwb triggers an indirect read operation. the data read from the control pages is stored in the itse indirect data register after the busy bit has cleared. busy the indirect access status bit (busy) reports the progress of an indirect access for the itse block. busy is set to logic 1 when this register is written, triggering an access. it remains logic 1 until the access is complete at which time it is set to logic 0. these registers should be polled to determine when new data is available in the itse indirect data register or when another write access can be initiated. the busy bit shows a default of ?x?. this does not require the bit to be cleared after a reset since the bit resets to 0 a few clock cycles after a reset. the bit is undefined for a short period (a few clock cycles) after a reset but the user will never read ?1? as the bit would clear before the bit is queried.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 document id: pmc-1991258, issue 7 register 0na9h: port set #1 - #16, etse indirect data bit type function default bit 15 unused x bit 14 unused x bit 13 r/w echar_ovwr[1] 0 bit 12 r/w echar_ovwr[0] 0 bit 11 r/w reserved[1] 0 bit 10 r/w reserved[0] 0 bit 9 r/w ecovd[9] 0 bit 8 r/w ecovd[8] 0 bit 7 r/w tsin[3]/ecovd[7] 0 bit 6 r/w tsin[2]/ecovd[6] 0 bit 5 r/w tsin[1]/ecovd[5] 0 bit 4 r/w tsin[0]/ecovd[4] 0 bit 3 r/w ecovd[3] 0 bit 2 r/w ecovd[2] 0 bit 1 r/w dinsel[1]/ecovd[1] 0 bit 0 r/w dinsel[0]/ecovd[0] 0 these registers contain the data read from the control pages after an indirect read operation or the to be data written to the control pages in an indirect write operation for etse blocks #1 through #16. dinsel[1:0] the data input select (dinsel[1:0]) bits report the etse input port identifier read after an indirect read operation has completed for the etse block. the input port identifier to be written to the control pages must be set to dinsel[1:0] before tri ggering a. dinsel[1:0] reflects the last value read or written until the completion of a subsequent indirect read operation. dinsel[1:0] also doubles as ecovd[1:0] tsin[3:0] the sts-1/stm-0 input time slot (tsin[3:0]) bits report the time-slot number read after an indirect read operation has completed. the time-slot number to be written to the control pages must be set up in this register before triggering a write. tsin [3:0] reflects the last value read or written until the completion of a subsequent indirect read operation. time slots #1 to #12 are valid. writing an invalid time-slot value results in undefined behavior. tsin[3:0] also doubles as ecovd[7:4].
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 document id: pmc-1991258, issue 7 tsin[3:0] sts-1/stm-0 time slot # 0000 invalid time slot 0001-1100 time slot #1 to time slot #12 1101-1111 invalid time slot ecovd[9:0] the character overwrite data bits (ecovd[9:0]) reports the data read after an indirect read operation has completed. the data to be written to the control pages must be set up in this register before triggering a write. ecovd[9:0] reflects the last value read or written until the completion of a subsequent indirect read operation. ecovd[9:0] represents the data written to the dinsel port/ tsout timeslot of the etse block provided the echar_ovwr[1:0] bits are logic b?11. otherwise, dinsel and tinsel control the output for the specified port/timeslot. reserved[1:0] the reserved[1:0] bits must be set as shown for correct operation of the tse. echar_ovwr[1:0] the character overwrite data insertion control bits (echar_ovwr[1:0]) report the value of the echar_ovwr[1:0] bits read after an indirect read operation has completed. the value of the echar_ovwr[1:0] bits to be written to the control pages must be set up in this register before triggering a write. echar_ovwr[1:0] reflects the last value read or written until the completion of a subsequent indirect read operation. the value of the echar_ovwr[1:0] bits control the source of the data bits that the muxing block outputs. when set to logic b?00 the muxing block samples and reorders the holding buffers. when set to logic b?11 then muxing block directly outputs the idle data (ecovd[9:0]). echar_ovwr values of ?b01 and ?b10 are invalid.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 document id: pmc-1991258, issue 7 register 0naah: port set #1 - #16, etse configuration bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r eactive x bit 2 r/w epsel 0 bit 1 r/w ej0rordr 0 bit 0 r/w ecoape 0 these registers provide page selection, active page indication, j0 reordering mode, and interrupt masking control for etse blocks #1 through #16. ecoape the change of active page interrupt enable bit (ecoape) masks the contribution of the change of active page event indication bit (e coapi) in the etsi block to intb. when ecoape is high, intb is asserted low when ecoapi is high. intb is not affected by the value of ecoapi when ecoape is low. ej0rordr the egress j0 reorder bit controls the reordering of j0/z0 bytes in the four sts-12 datastreams through the n th etse block. time slot interchange of the j0/z0 bytes in the n th etse is suspended when j0/z0 reordering is disabled. when ej0rordr is set low, the j0/z0 bytes are not reordered. when ej0rordr is set high, j0/z0 byte reordering is enabled. if j0 reordering is enabled, j0 masking should also be enabled in all r8fas to prevent k28.5 characters from being switched to a position other than j0. j0 masking is done using the j0mask bit in register 0n80h , 0n88h, 0n90h, and 0n98h, for 0<= n <= 15.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 document id: pmc-1991258, issue 7 epsel the page select (epsel) bit is used in the selection of the current active. this bit is logically xored with the value of the cmp signal to dete rmine which control page is currently active. if the xor result is logic 1, control page 1 is selected. otherwise, control page 0 is selected. eactive the active page indication (eactive) bit indicates which control page is currently active in the associated muxing blocks. when this bit is logic 0 then page 0 is active. when this bit is logic 1 then page 1 is active.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 document id: pmc-1991258, issue 7 register 0nabh: port set #1 - #16, etse interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r ecoapi x these registers provide the interrupt status of etse blocks #1 through #16. ecoapi the change of active page interrupt (ecoapi) reports a change in the active page event for the itse. ecoapi is set high when a change of active page has occurred since the last clear for the register. ecoapi is cleared on a read to this register when wcimode is logic 0. ecoapi is cleared on a write of logic 1 to ecoapi when wcimode is logic 1. intb is asserted low when both ecoape and ecoapi are high. if ecoape is asserted, ecoapi must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 document id: pmc-1991258, issue 7 register 0nb0h, 0nb8h, 0nc0h, 0nc8h: port set #1 - #16, t8de #1 - #4 control and status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w j0ins 0 bit 4 r/w fifoerre 0 bit 3 r/w tpins 0 bit 2 r/w reserved 0 bit 1 w center 1 bit 0 r/w dlcv 0 these registers provide control and report the status of t8de blocks #1 through #64. dlcv the diagnose line code violation bit (dlcv) controls the insertion of line code violations in the outgoing data stream. when dlcv is logic 1, the encoded data is continuously inverted and will result in a varying number of line code violations at the receiver depending on its configuration. an immediate line code violation is generated since an incorrect disparity character is transmitted. as long as dlcv is set, further line code violations will be transmitted following the transmission of an telecombus control character. note that telecombus control characters are not affected by the dlcv bit but are passed unaltered. this results in a continuous stream of disparity errors in a receiving r8fa while dlcv is high. note that this stream of disparity errors will eventually saturate the lcv[15:0] counters in the receiving device. when dlcv is logic 0, no code inversion is performed.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 document id: pmc-1991258, issue 7 center: the fifo centering control bit (center) cont rols the separation of the t8de fifo read and write pointers. center is a write only bit. when a logic high is written to center, and the current fifo depth is not in the range of 3, 4 or 5 characters, the fifo depth is forced to be 3 or 4 8b/10b characters deep, with a momentary data corruption. writing to the center bit when the fifo depth is in the 3, 4 or 5 character range produces no effect. center always returns a logic low when read. reserved the reserved bit must be set to the indicated default value for correct operation of the tse. tpins the test pattern insertion (tpins) controls the insertion of test pattern in the outgoing data stream for jitter testing purpose. when this bit is set high, tp[9:0] in the t8de test pattern register is selected for output. tpins takes precedence over j0ins, inserted k28.5 will be overwritten with the test pattern. fifoerre the fifo underrun/overrun error interrupt enab le bit (fifoerre) masks the contribution of the fifo underrun/overrun event indication bit (fifoerri) in the t8de block to intb. when fifoerre is high, intb is asserted low when fifoerri is high. intb is not affected by the value of fifoerri when fifoerre is low. j0ins the j0 byte insertion (j0ins) controls the inse rtion of first j0 bytes in the outgoing data stream. when this bit is set to logic 1, a k28.5 character is inserted at the j0 byte position on every frame, overwriting the data in that position (tse inserted ais included). when j0ins is set to logic 0, the outgoing data stream is not modified.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 document id: pmc-1991258, issue 7 register 0nb1h, 0nb9h, 0nc1h, 0nc9h: port set #1 - # 16 t8de #1 - #4 interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r fifoerri 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x these registers report the interrupt status for t8de blocks #1 through #64. fifoerri the fifo overrun/underrun error interrupt indication bit (fifoerri) reports a fifo overrun/underrun error event. fifoerri is set high when fifo logic detects fifo read and write pointers in close proximity to each other. fifoerri is cleared on a read to this register when wcimode is logic 0. fifoerri is cleared on a write of logic 1 to fifoerri when wcimode is logic 1. intb is asserted low when both fifoerre and fifoerri are high. if fifoerre is asserted, fifoerri must be cleared before intb will be reasserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 document id: pmc-1991258, issue 7 register 0nb4h, 0nbch, 0nc4h, 0ncch: port set #1 - #16 t8de #1 - #4 test pattern bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r/w tp[9] 1 bit 8 r/w tp[8] 0 bit 7 r/w tp[7] 1 bit 6 r/w tp[6] 0 bit 5 r/w tp[5] 1 bit 4 r/w tp[4] 0 bit 3 r/w tp[3] 1 bit 2 r/w tp[2] 0 bit 1 r/w tp[1] 1 bit 0 r/w tp[0] 0 these registers store the test pattern for test pattern insertion for t8de blocks #1 through #64. tp[9:0] the test pattern register (tp[9:0]) for t8de block #x contains the test pattern conditionally inserted into output data stream #x. tp[9:0] is inserted into the output data stream when the tpins bit is set high.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 document id: pmc-1991258, issue 7 register 0nb5h, 0nbdh, 0nc5h, 0ncdh: po rt set #1 - #16, txlv and piso control bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 r/w reserved[8] 0 bit 10 r/w reserved[7] 0 bit 9 r/w reserved[6] 0 bit 8 r/w txlv_enb 0 bit 7 r/w piso_enb 0 bit 6 r/w reserved[5] 0 bit 5 r/w reserved[4] 0 bit 4 r/w reserved[3] 0 bit 3 r/w reserved[2] 0 bit 2 r/w reserved[1] 1 bit 1 r/w reserved[0] 1 bit 0 r/w arstb 1 these registers control the operation of lvds transmit and piso blocks #1 through #64 arstb the analog reset bit (arstb) resets the associ ated txlv and piso blocks. when arstb is set to logic 0, the txlv and piso are reset. reserved[8:0] the reserved[8:0] bits must be set to the indi cated default value for correct operation of the tse. piso_enb the piso enable bit (piso_enb) controls the op eration of the piso block. piso_enb is set to logic 1 to disable the piso block. piso_enb is set to logic 0 to enable the piso block.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 document id: pmc-1991258, issue 7 txlv_enb the txlv enable bit (txlv_enb) controls th e operation of txlv block. txlv_enb is set to logic 1 to disable the txlv block. txlv_enb is set to logic 0 to enable the txlv block.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 document id: pmc-1991258, issue 7 11 test features description simultaneously asserting (low) the csb, rdb and wrb inputs causes all digital output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the tse. test mode registers (as opposed to normal mode registers) are selected when trs (a[12]) is high. in addition, the tse also supports a standard ieee 1149.1 five-signal jtag boundary scan test port for use in board testing. all digital device inputs may be read and all digital device outputs may be forced via the jtag test port.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 document id: pmc-1991258, issue 7 11.1 jtag test port the tse jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section. table 14 instruction register (length ? 3 bits) instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 table 15 identification register length 32 bits version number 1h part number 5372h manufacturer?s identification code 0cdh device identification 153720cdh table 16 boundary scan register length ? 57 bits pin/ enable register bit cell type i.d. bit pin/ enable register bit cell type i.d. bit tj0fp 0 out_cell oeb_d(13) 29 out_cell 0 hiz 1 out_cell d(12) 30 io_cell 0 vss 2 out_cell oeb_d(12) 31 out_cell 1 intb 3 out_cell d(11) 32 io_cell 1 ale 4 in_cell oeb_d(11) 33 out_cell 0 wrb 5 in_cell d(10) 34 io_cell 0 rdb 6 in_cell oeb_d(10) 35 out_cell 0 csb 7 in_cell d(9) 36 io_cell 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 document id: pmc-1991258, issue 7 pin/ enable register bit cell type i.d. bit pin/ enable register bit cell type i.d. bit cmp 8 in_cell oeb_d(9) 37 out_cell 0 a(12) 9 in_cell d(8) 38 io_cell 1 sysclk 10 in_cell oeb_d(8) 39 out_cell 0 rj0fp 11 in_cell rstb 40 in_cell 0 a(11) 12 in_cell d(7) 41 io_cell 1 a(10) 13 in_cell oeb_d(7) 42 out_cell 1 a(9) 14 in_cell d(6) 43 io_cell 1 a(8) 15 in_cell oeb_d(6) 44 out_cell 0 a(7) 16 in_cell d(5) 45 io_cell 1 a(6) 17 in_cell oeb_d(5) 46 out_cell 1 a(5) 18 in_cell d(4) 47 io_cell 0 a(4) 19 in_cell oeb_d(4) 48 out_cell 0 a(3) 20 in_cell d(3) 49 io_cell 1 a(2) 21 in_cell oeb_d(3) 50 out_cell 0 a(1) 22 in_cell d(2) 51 io_cell 1 a(0) 23 in_cell oeb_d(2) 52 out_cell 0 d(15) 24 io_cell d(1) 53 io_cell 1 oeb_d(15) 25 out_cell 1 oeb_d(1) 54 out_cell 0 d(14) 26 io_cell 0 d(0) 55 io_cell 0 oeb_d(14) 27 out_cell 1 oeb_d(0) 56 out_cell 0 d(13) 28 io_cell 1 notes: oeb_d[15:0] is the active low output enable for d[15:0]. when set high, intb will be set to high impedance. hiz is the active low output enable for all out_cell types except oeb_d[15:0], and intb tj0fp will be the first bit to appear on tdo when the scan chain is shifted out. 11.1.1 boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherw ise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table located above.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 document id: pmc-1991258, issue 7 figure 8 input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 figure 9 output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 document id: pmc-1991258, issue 7 figure 10 bi-directional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 11 layout of output enable and bi-directional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 document id: pmc-1991258, issue 7 12 operation there are several important aspects regarding the operation of tse-based cross-connect fabrics; these are dealt with in turn in the following sections. 12.1 power conservation in order to realize power savings, unused lvds links may be disabled individually. this is accomplished by setting the rx_enb and dru_enb to logic ?1? for the receive channels, and by setting the txlv_enb and piso_enb register s to logic ?1? for the transmit channels. for greater power savings, each face (group of 16 links) of the tse can be powered down individually if none of the lvds links are in use. in addition to disabling the receive and transmit channels for the face, setting the csu_enb regist er bit to logic ?1? will idle the corresponding csu, which will greatly reduce power. the power reductions are summarized in the following table: table 17 power reduction for disabled links power reduction (in mw) block control bit vddi avdl avdh remarks txlv tx_enb=1 0 0 54 rxlv rx_enb=1 0 5 7 dru dru_enb=1 16/20 0 0 16 mw if the csu is active, otherwise 20 piso piso_enb=1 10 0 0 csu csu_enb=1 0 350 50 bi-directional link 26 5 61 txlv, rxlv, dru, and piso disabled face 480 430 1026 16 links, csu disabled note: these power reductions are approximate and have not been characterized.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 document id: pmc-1991258, issue 7 12.2 lvds optimizations the lvds interface implemented on the tbs and tse follows the ieee 1596.3-1996 specification with some minor exceptions. the changes are implemented to customize and optimize the lvds interface for the system and are described in detail below. even with these differences the lvds interface should be compatible with the physical layer of other lvds interfaces. the differences from the ieee specification include: 1. faster rise/fall times (200 ? 400) ps versus the specified (300 ? 500) ps. faster edge rates are commonly used with higher speed lvds interface s in the industry to ease the interfacing. the ieee 1596.3-1996 edge rates are optimized for data rates below 400 mbps hysteresis is not implemented in the receive lvds interface. 2. hysteresis is used in many implementations to negate the effect of noise that may exist on unused lvds links. hysteresis was not implemented in the chess? set devices to minimize circuit complexity, power and cost. instead, the rx interfaces and the drus for unused links can be disabled (powered down) through register control in order to prevent sensitivity to noise on these links 3. the lvds transmitter contains an on-chip 100-ohm termination. most implementations have single 100-ohm termination on the receiver. by implementing a double termination (on both the lvds receiver and transmitter) a higher signal integrity and matching is ensured. 4. although not a difference with the layer 1 ieee 1596.3-1996 specification, the layer 2 8b/10b encoding is discussed here for complete ness. 8b/10b encoding guarantees transition density as compared to scrambled encoding, which provides only a certain probability of transition density. this guaranteed transition density allows a simpler and more power- effective data recovery unit, provides a more robust serial interface (greater trace or back- plane distance achievable). it also negates the need for complete sonet framing since the a1a2 and j0 bytes can be encoded into special escape characters of the lvds data stream. 5. the device uses 20% resistors; not 10% as specified by the lvds specification. they are 20% resistors since that was the highest tolerance resistor available for on-chip applications. however, because they are integrated on-chip, this lvds interface can achieve much better signal integrity than one with off-chip terminations.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 document id: pmc-1991258, issue 7 12.3 lvds hot swapping the lvds electrical interface differs from a standard cmos interface; there is no inherent problem in leaving the lvds inputs floating. note that the lvds receiver consists of a differential amplifier with a wide common-mode ra nge. the power dissipation is independent of the data transitions (that is, if the input is connected). there is an internal 100 termination across the positive and negative input. floating inputs will settle to an ar bitrary voltage (between vdd and vss) determined by leakage paths. regardless of this arbitrary voltage, the input structure of the receiver will operate in its proper range and the receiver output will be logic 1 or 0 depending on internal offsets. noise events (power supply noise, crosstalk) may induce the receiver to toggle randomly, generating "ambiguous" data. unused links should be disabled in software. th is will ensure that the power consumption for those links will be reduced to nearly 0 mw. there is no requirement for how quickly the link should be disabled. disabling the link simply results in lower power dissipation since the circuitry will be shut down. this action is not mandatory, but is good practice. during a hot-swapping situation, there will be no electrical damage on the lvds inputs provided that maximum ratings are not exceeded (see absolute maximum ratings section 14) . the ?hot- swap? channel can be left enabled and the device will sync up once the far end transmitter is connected. there are no effects on other channels. hot swapping of cards is still allowed by reprogramming of the links in software. 12.4 lvds trace lengths the tse utilizes 64 different input and output differential lvds pairs. it is critical to match the lengths of the positive and negative traces of each differential pair to minimize skew and maximize the eye opening. however, matching one differential pair to another pair is not as important. the high-speed serial lvds links are connected to a 24 word (10 bit byte) fifo. of this 24 word fifo, 8 words should be allocate d for clock skew and wander between cards or within devices. the remaining 16 words are th en available to accommodate clock skew and wander between cards or within devices, along wi th differences in trace lengths between lvds pairs. the 16 word fifo yields an allowable inter-link de lay differential of 205.8 ns or 41.2m. this is calculated as follows: 16 words x 10 bits/word = 160 bits of margin in fifo 1/(777.6 mb/s) = 1.29 ns/bit on the serial link 160 bits x 1.29 ns/bit = 205.8 ns of margin = 16 clock cycles (at 77.76 mhz)
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 document id: pmc-1991258, issue 7 a transmission speed of 2/3 the speed of light, this corresponds to a trace length difference of 41.2m: 205.8x10 9 s x 2/3 x 3x10 8 m/s = 41.2 m however, it is important to note that the lvds interface itself is designed to drive 1m of backplane plus only 30cm of trace length on either side. since this 1.6m of trace length is smaller than the maximum trace length differential computed above, the tse?s ability to tolerate trace length differential will not be a limiting factor for designs. the total available trace length of 1.6m corresponds to 8ns of delay or a worst case difference of 0.6 clock cycles (77.76 mhz) between any two lvds links. low loss cable or an optical interface can be used to connect to the lvds interface to realize greater back-plane distances. 12.5 jtag support the tse supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset th e tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 document id: pmc-1991258, issue 7 figure 12 boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and ge nerates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single-bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 document id: pmc-1991258, issue 7 the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs. 12.5.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controll ed using primary input, tms. the finite state machine is described below.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 document id: pmc-1991258, issue 7 figure 13 tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 document id: pmc-1991258, issue 7 12.5.2 states test-logic-reset the test logic reset state is used to disable th e tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state the instruction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register?s parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register?s parallel output latches are used to control the device?s outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 document id: pmc-1991258, issue 7 update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. boundary scan instructions the following is a description of the standard instructions. each instruction selects a serial test data register path between input, tdi and output, tdo. 12.5.3 instructions bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is place between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundar y scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device?s identification code can then be shifted out using the shift-dr state.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 document id: pmc-1991258, issue 7 stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out output, tdo using the shift-dr state. 12.6 initialization procedure the following is a suggested initialization procedure which may be helpful when writing initialization code for the tse. set the tse master configuration register to: etse_mode=0, itse_mode=0, set addr 002h to 8400h set the csu control registers to: csu_enb=0, csu_rstb=1 set addresses 0020h, 0024h, 0028h, 002ch to 0409h set the sswt rj0fp delay register 0040h as per section 1.1 set the sswt tj0fp delay register 0047h as per section 1.1 set the r8fa 1 ? 64 analog control re gister to: dru_enb=0, rx_enb=0 and dru_control=1101 set addresses 0n83h, 0n8bh, 0n93h, an d 0n9bh (n=0 to f) to cc34h set the itse 1- 16 time slot switching settings as per switching requirements. set the etse 1-16 time slot switching settings as per switching requirements. set the sswt 1-16 space switching settings as per switching requirements. set the t8de 1 ? 64 analog control re gisters to: txlv_enb=0, piso_enb=0 set addresses 0nb5h, 0nbdh, 0nc 5h, and 0ncdh (n=0 to f) to 0007h ensure that the csus show stable ?locked? status by reading registers 0x21/0x22, 0x25/0x26, 0x29/0x2a and 0x2d/0x2e: read registers 0x21, 0x25, 0x29 and 0x2d ? expect to see 0x01 representing the interrupt from changes in lock state during reset. read registers 0x21, 0x25, 0x29 and 0x2d again ? expect to see 0x00 indicating stable lock status. read registers 0x22, 0x26, 0x2a and 0x2e ? expect to see lockv bit set to 1 indicating that the csus are stable in the locked state.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 document id: pmc-1991258, issue 7 after the csus have locked, the transmit fifos must be re-centered since they will have suffered over-run or under-run conditions while the csus were not locked. to re-center the fifos, write a 1 to the center bit in all 64 of the t8de control and status registers (0nb0h, 0nb8h, 0nc0h, and 0nc8h where n=0 to f). enable all interrupts on the device by writing registers as follows: cstr 1 ? 4 addr 0021h, 0025h, 0029h, and 002dh to ---------------1b sswt addr 0043h to ---------------1b r8fa 1- 64 addr 0n80h 0n88h, 0n90h, 0n 08h (n=1 to 15) to -------- 1111----b itse 1- 16 addr 0na2h (n=0 to 15)to 00001h etse 1- 16 addr 0naah (n=0 to 15)to 00001h t8de addr 0nb0h, 0nb8h, 0nc0h, 0nc8h to -----------1----b 12.7 interrupt service routine the tse will assert intb to logic 0 when a condition that is configured to produce an interrupt occurs. to find which condition caused this interrupt to occur, the procedure outlined below should be followed: read the registers 0003h ? 000eh to find the fu nctional block(s) which caused the interrupt. find the register address of the corresponding block that caused the interrupt and read its interrupt status registers. the interrupt functional block and interrupt source identification register bits from step 1 are cleared once these register(s) have been read and the interrupt(s) identified. service the interrupt(s). if the intb pin is still logic 0, then there are still interrupts to be serviced and steps 1 to 3 need to be repeated. otherwise, all interrupts have been serviced. wait for the next assertion of intb. 12.8 interpreting the status of receive decoders the receive decoder blocks (r8fa) produce interrupts based on four receiver conditions or events: oca (out of character alignment), ofa (out of frame alignment), fuo (fifo underrun/overrun) and lcv (line code violatio n). understanding the relationships between these conditions can help to diagnose device status. these conditions have the following inter- relationships:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 document id: pmc-1991258, issue 7 oca implies ofa until character alignment is re-achieved. oca will most likely cause some lcvs but not necessarily a continual stream of them. since character boundaries are not known, framing and disparity are effectively meaningless anyway. ofa, by itself, does not cause any of the other conditions. fuo may produce zero, one or many lcvs, depending on how the fifo overrun/underrun occurs. persistent lcvs (five or more in any sequence of 15 characters) cause oca. 12.9 accessing indi rect registers indirect registers are used to conserve address space in the tse. writing the indirect address register accesses indirect registers. the following steps should be followed for writing to indirect registers: read the busy bit. if it is equal to logic 0, co ntinue to step 2. otherwise, continue polling the busy bit. write the desired configurations for the channel into the indirect data registers. write the channel number (indirect address) to the indirect address register with rwb set to logic 0. read busy. once it equals 0, the indirect write has been completed. the following steps should be followed for reading indirect registers: read the busy bit. if it is equal to logic 0, co ntinue to step 2. otherwise, continue polling the busy bit. write the channel number (indirect address) to the indirect address register with rwb set to logic 1. read the busy bit. if it is equal to logic 0, con tinue to 4. otherwise, continue polling the busy bit. read the indirect data registers to find the state of the register bits for the selected channel number. 12.10 using the perfor mance monitoring features the performance monitor counters within the tse are the r8fa line code violation counters. the counters will saturate and not roll over if they reach their maximum value.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 document id: pmc-1991258, issue 7 a device update of all the counters can be achieved by writing to the tse master clock activity and accumulation trigger register (0001h). the tip bit in the tse master clock activity and accumulation trigger register can be polled to determine when all the counter values have been transferred and are ready to be read. 12.11 ?j0? synchronization of the tse in a chess system any tse/tbs fabric can be viewed as a collection of different stages. for example, a time- space-time switch could be constructed with five datapath stages: 1. ingress load devices (e.g. spectra-2488?) 2. ingress tbs devices 3. tse devices 4. egress tbs devices 5. egress load devices (e.g. spectra-2488) note that in some cases, one physical device may serve in two stages, such as stages 1 and 5 or stages 2 and 4. sts-12 frames are pipelined through this fabric in a regular fashion, under control of a single clock frequency (77.76 mhz). in order to maintain valid framing for the group of sts-12 streams, the datapath devices must be coordinated with one another. the first step in this coordination is the use of a global frame synchronization pulse to mark the position of frame boundaries as they enter the fabric. however, since each device in the system datapath sees the sts-12 frames at a different latency than other devices, there must be a mechanism to account for the individual latencies at different points along the datapath. the most significant source of delay is the cumulative latency of the devices that lie along the system datapath. to accommodate different syst em arrangements, a synchronization frame pulse and a programmable frame delay register are used to re-frame the sts-12 streams for each system datapath device. in the tse, this fifo is 24-words deep and is controlled by the rj0fp pin along with the rj0dly register. this frame de lay register is used to inform the tse of the latency between a frame pulse on the rj0fp pin and the presence of j0 characters in the fifos so that a re-framing mechanism can be triggered at the appropriate time. because the j0 characters may lie at different fifo depths, due to skew be tween links, this re-framing can be achieved by realigning the fifo read pointers to match the j0 positions.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 document id: pmc-1991258, issue 7 in addition to device latencies, there are other sources of delay. furthermore, these delays may vary from link to link. for example, clock skew or differential trace lengths impose uneven delays on individual links. the 24-word depth of the fifos allows these delays to be equalized as part of the re-framing process. when the rj0fp-rj0dly trigger signals the occurrence of a frame boundary, the tse will adjust the fifos read positions to realign the sts-12 streams? j0 characters with one another. as long as the j0 characters from all the sts-12 streams are indeed simultaneously present in their respective fifos when this occurs, the tse will effectively re- align the streams as part of the re-framing process. the large fifo depth allows the tse to compensate for such differential delays as trace lengths that vary by several meters. smaller delay variances, such as those due to clock jitter, can be absorbed automatically by the serial receive links. if they prove to be too large for such absorption, they will then be corrected through the fifo re-framing process. in order to guarantee that the rj0fp-rj0dly trigger will happen when all streams? j0 characters are simultaneously present within the fifos, it is important to choose correct values for the frame delay register. the following example explains how frame delay register values are chosen for the devices of a sample system. consider the implementation shown in figure 14. all devices receive the global frame pulse simultaneously at time t0 (ignoring any trace length differentials). the spectra-2488 emits the j0 byte onto the telecombus upon receiving the global frame pulse on the dj0ref input. this action is entirely independent of receiving a j0 byte from the optical line. spectra-2488 pointer adjustments wi ll define the start of the payload envelope (the j1 byte indicates start of payload) and this payload will be outputted over the telecombus. the spectra-2488 can be viewed as the master by which the synchronization of the other chess devices is determined. the tbs expects the four incoming eight bit 77.76 mhz telecombus data paths to be synchronized and upon processing emits the serialized data with j0 character 33 clock cycles after receiving the j0 on the parallel telecombus. the j0 byte on each of the twelve independent 777.6 mhz lvds links are not exactly simultaneous and may have a slight amount of skew relative to each other (because of presence of an 8 word fifo on the lvds transmitter output). the lvds links are th en mated to the tse through a back-plane. the tse is programmed (via indirect register access of the rj0dly[13:0] word) to expect the j0 byte a certain number of clock cycles after it receives the global frame pulse.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 document id: pmc-1991258, issue 7 the ingress fifos permit a variable latency in j0 arrival of up to 16 clock cycles. that is, the largest tolerable delay between the slowest and fastest lvds link of the 64 tse lvds links is 16 bytes. consequently, the external system must ensure that the relative delays between all the 64 receive lvds links be less than 16 bytes. the minimum value for the internal programmable delay (rj0dly[13:0]) is the delay to the last (slowest) j0 character plus 15 bytes. the maximum value is the delay to the first (fastest) j0 character plus 31 bytes. the actual programmed delay should be based on the delay of the ?slowest? of the 64 links ? the link in which j0 arrives last plus a small safety margin of 1 or 2 words. the magnitude of the clock cycle delay is bounded by two parameters. first, the programmed delay register rj0dly is 14 bits. this implies that a clock cycle delay of 214 ?1 or 16,383 clock cycl es can be programmed. however, the second parameter, the frame rate (125 s), bounds the delay to one sts-12 frame or 9719 (9719 unique values) clock cycles (125 s x 77.76 mhz), after which the next sonet frame begins. the tse, upon receiving the global frame pulse, will wait th e programmed amount of time (56 clock cycles + cable length delays) before prompting each of the 64 links to emit their j0 character. the number of clock cycles can be determined by simply adding the relevant device and cable length latencies. this synchronization mechanism is flexible enough to accommodate system paths with different cumulative device latencies. consider a tse that is mated to a s/uni-mach48 on one link and a spectra-2488 feeding a tbs on the other link. the alternate data paths have different delays; the spectra-2488/tbs link has a greater delay than the s/uni-mach48 link delay. in this case, the s/uni-mach48 is programmed to emit the j0 pulse later than spectra-2488 (but aligned with the tbs serial output) such that the j0 from both sources arrive at the tse within the allowed 16-clock cycle window. the s/uni-mach48 programmed delay is 24 clock cycles after the receipt of the frame pulse.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 document id: pmc-1991258, issue 7 figure 14 ?j0? synchronization control in the line side rx direction: 1. an 8khz frame pulse is received by all devices at time t 0 2. upon receipt of the 8khz frame pulse, the spectra- 2488 outputs data (and j0) onto the telecombus at time t 0 3. the tbs emits the serialized j0 8b/10b character approximately 35 clock cycles later at time t 1 4. the j0 character arrives at the input of the tse a clock cycles later at time t 2 . a and b represents the clock cycle delay of the links. 5. the tse rj0dly value can be set to create a receive fifo depth of approximately half the fifo length of 24 characters. the j0 character w ill be in the fifo al ong with 11 more characters approximately 23 clock cycles after the j0 character enters the tse input. the cumulative time in sysclk cycles from t 0 to t z plus the extra 23 clock cycle delay into the tse receive fifo is the the time that should be used for the rj0dly value. 6. the tse emits the j0 characters approximatel y 43 clock cycles after the j0 characters are read out of the receive fifos (t 0 + rj0dly) at time t 3 . 7. the j0 character is present at the mach48 device b clock cycles later at time t 4 8. the s/uni-mach48 rj0dly value should be set using the same method as used to set the tse rj0dly value. (rj0dly = j0 characte r arrival time + 23 clock cycles to f ill the receive fifo halfway. in the line side tx direction: 1. an 8khz frame pulse is received by all devices at time t 0 2. approximately 7 + oj0ref sysclk cycles after receiveing the the 8 khz frame pulse on oj0ref, the s/uni-mach-48 outputs the j0 characte r to the tse device . since the arrival of j0 characters at the tse receivers from the tbs and the s/uni-mach-48 must be aligned, the oj0refdly value at the s/uni-mach28 should be set to the cumulative latency of the tbs in sysclk cycles (33-36) minus the 7 delay between oj0ref and the j0 character output when oj0refdly=0. 3. the tse outputs the j0 character at time t c 4. the tbs receives the j0 character at time t d . approximately 23 clock cycles following the arrival of the j0 character, the tbs receive fifo will be half full. the cumulative time from t 0 to t d in sysclk cycles plus the additi onal 23 cycle delay into the tbs receive fifos should be used for the tbs rj0dly value. note: in all cases j0 character arrival times specified are the nominal arrival times. this is because the tx fifo can impose a +/-4 cycle delay on the data. the nominal time assumes the additional delay by the tx fifo imposed is 0 cycles in all cases. the calculated rj0dly values provided in the example will work in any case - the receive fifos may just be more or less full than stated (12 characters full), depend ing on the state of the upstream tx fifo. 23 spectra- 2488 dj0ref aj0j1 dj0j1 tbs rj0fp oj0j1 ij0j1 tse rj0fp s/uni-mach48 rj0fp oj0ref parallel telecombus serial lvds telecombus serial lvds telecombus 8 khz reference frame pulse distributed to all devices at t 0 t o t 1 t 2 t 3 t 4 t a t b t c t d t e t o 35 t 1 t 2 a t 3 t 4 b t b t c b t a a t d t e 23 rj0dly tse 23 rj0dly mach rj0dly tbs 28 oj0refdly mach 46 rx direction tx direction 43
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 document id: pmc-1991258, issue 7 12.12 synchronized control setting changes the tse supports dual switch control settings. these dual settings permit one to be operational while the other is updated as a result of some new connection requests. the cmp input selects the current operational switch control settings. cmp is sampled by the tse on the base timing pulse t. the internal blocks sample the registered cmp value as they receive the next j0 character ?at least a delay of rj0dly. the new cmp value is applied on the first a1 character of the second following sts-12 frame. this switchover is hitless; the control change which does not disrupt the user data flow in any way. this feature is required for the addition of arbitrary new connections, as existing connections may need to be rerouted (see the discussion of the connection routing algorithm in this document). 12.13 fabric rules of composition. there are rules governing how the tse, the tbs, the load devices (spectra-2488, spectra-4x155, and s/uni-mach48), can be combined to form legal fabrics. a hypothetical load device with an on-board tbs is also considered. this section describes the interconnecting buses, gives a behavioral description of the four components, lists the rules of composition for fabric formation, and gives several examples of legal fabrics. 12.13.1 interconnections the various components communicate via two full-duplex channel types: parallel telecombuses (p-tcb) and serial telecombuses (s-tcb). th e s-tcbs are always point-to-point. the p- tcbs can be either point-to-point, or can be combined with one stage of wired-or multiplexing. both buses carry 4*sts-12 = sts-48 streams (i.e., they can be thought of as a single sts-48 flow, or as four independent sts-12 flows ? the tse will always treat each sts-1 independently in any case.) in the diagrams below, p-tcbs are drawn as heavy directed arrows; s-tcbs are drawn as lighter arrows. 12.13.2 behavioural descriptions of components load: load devices (spectra-2488) have one full-duplex p-tcb port. we ignore the line side of these devices. loads are represented in figure 15. tbs: tbs devices have one p-tcb port and three s-tcb ports. the tbs can take any of 3*48 sts-1s from the ingress s-tcbs and place it in any of 48 sts-1 slots in the egress p-tcb. in the other direction, the tbs can fill any of the 3*48 egress s-tcb slots with any sts-1 taken from the ingress p-tcb. tse: tse devices have 64 full-duplex s-tcb ports. the tse implements a full time:space:time switching function, as described in this document.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 document id: pmc-1991258, issue 7 each component emits synchronized sts frames with a time delay controlled by the timing signal described in the ?j0 synchronization? sect ion. these timing signals are indicated by the arrows directed at the egress ports of each component. figure 15 fabric components load tbs tse load p-tcb load s-tcb load p-tcb/s-tcb tbs s-tcb tse (heavy data flow lines are p-tcbs; light data flow lines are s-tcbs; arrows to data flow lines are timing controls). 12.13.3 rules of composition no connections other than egress p-tcb to ingress p-tcb and egress s-tcb to ingress s-tcb are permitted. each tse fabric must have a central column (or multiple columns) of tse devices through which all traffic is switched. all traffic must arrive at the central tse column at the same time (with respect to sts-12 frames).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 document id: pmc-1991258, issue 7 all paths from any load?s egress p-tcb to any load?s ingress p-tcb must traverse sequences that are identical in time and components as they pass through the tse core. where the common core path extends out to the load devices, this rule includes paths from any load a to any load b, the reverse paths from b to a, a nd any self-loops from a to a or b to b. as mentioned below, some loads may be further from the core, their paths being extended by the use of extra tse devices which serve as gather/scatter devices for low aggregate bandwidth loads. these extended path portions need not be identical to other paths, but they must be traversed before and after the common core paths. time delays on all longest simplex paths must begin with zero at the source load (the longest paths are those paths that are extended, if any. normally, all paths are ?longest? and all begin at time zero.). the time delays on all paths must be strictly increasing, and the delays on all path delays must be identical when they reach the tse core column. 12.13.4 examples of legal composition the following figures give examples of legal fabric compositions. appropriate time delays are indicated by monotonically increasing integers. figure 16 load:load null fabrics. load load p-tcb loads s-tcb loads load load 0 0 0 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 document id: pmc-1991258, issue 7 figure 17 tbs fabrics (non-redundant). tbs load 0 2 tbs load 0 2 tbs load 0 2 1 1 1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 document id: pmc-1991258, issue 7 figure 18 tse fabric (redundant). tbs load 0 3 tbs load 0 3 1 1 tse tse 2 2 where sts-12 and/or sts-3 devices are connected to tse fabrics, these same rules apply, but the tbs devices connect to multiple load devices. in multi-plane tse fabrics, tbs devices which service these lower rate devices serve as traffic distributors and collectors to permit sts- 12/3 samples to be switched to and from any sts-1 in the fabric. an example of the use of a tse as a gather/scatter device in an eight plane tse fabric is illustrated in figure 19 below. the point of this figure is to illustrate the need for unequal path lengths that meet at the same time in the tse core.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 document id: pmc-1991258, issue 7 figure 19 tse fabric with differing path lengths tse tse tse tse tse tse tse tse sts-192 load tse sts-48 load sts-48 load ... ...
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 document id: pmc-1991258, issue 7 13 functional timing 13.1 receive interface timing figure 20 below, shows the relative timing of the receive interface. the lvds links carry sonet/sdh frame octets that are encoded in 8b/10b characters. frame boundaries, justification events and alarm conditions are encoded in special control characters. the upstream devices sourcing the links share a common clock and have a common transport frame alignment that is synchronized by the receive serial interface frame pulse signal (rj0fp). due to phase noise of clock multiplication circuits and backplane routing discrepancies, the links will not phase aligned to each other but are frequency locked. the delay from rj0fp being sampled high to the first and last j0 character is shown in figure 20. in this example, the first j0 is delivered on link rn[x]/rp[x]. the delay to the last j0 represents the time when the all the links have delivered their j0 character. in the example below, link rn[y]/rp[y] is shown to be the slowest. the minimum value for the internal programmable delay (rj0dly[13:0]) is the delay to the last j0 character plus 15. the maximum value is the delay to the first j0 character plus 30. consequently, the external system must ensure th at the relative delays between all the receive lvds links be less than 16 bytes. the relative phases of the links in figure 20 are shown for illustrative purposes only. links may have different delays relative to other links than what is shown. figure 20 receive interface timing rp[ x ]/ rn[ x ] rn[ y ]/ rp[ y ] ... sysclk rj0fp s4,3/ a2 s1,1/j0 s2,1/ z0 s4,3/ a2 s1,1/j0 s2,1/ z0 rj0dly[13:0] delay ... ... ... ... ... max delay between first and last j0s max delay until internal frame pulse ... ... ... min delay until internal frame pulse
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 document id: pmc-1991258, issue 7 13.2 transmit interface timing figure 21 below shows the delay from assertion of rj0fp to the transmit serial data links. due to the presence of fifos in the data path, the delay to the various links can differ by up to 8 cycles. the minimum delay (rj0dly + 40 sysclk cycles) is shown to be incurred by one of the transmit serial data links (tp[ x ]/tn[ x ]). the maximum delay (rj0dly + 47 cycles) is shown to be incurred by another transmit serial data links (tp[ y ]/tn[ y ]). the suggested setting for tj0dly results in a tj0fp pulse at the time at which all the transmit serial links have transmitted their respective j0 characters. the maximum delay from rj0fp to the transmission of a j0 pulse is rj0dly + 47 cycles. therefore the suggested setting for tj0dly is rj0dly+ 47. the relative phases of the links in figure 21 are shown for illustrative purposes only. links may have different delays than what is shown. figure 21 transmit interface timing tp[ x ]/ tn[ x ] tn[ y ]/ tp[ y ] ... sysclk rj0fp s4,3/ a2 s1,1/j0 s2,1/ z0 s4,3/ a2 s1,1/j0 s2,1/ z0 rj0dly+ max delay(47 cycles) to last j0 ... ... rj0dly + min delay(39 cycles) to first j0 ... ... ... ... tj0fp ... figure 22 below shows the delay from cmp to the transmit serial data links. cmp is valid only at the rj0fp pulse time, whether rj0fp is pulsed or not. it is ignored at other locations in the transport frame. a change in value to the connection memory page signal (cmp) results in changing the active switch settings. given that cmp is sampled on the rj0fp pulse time 0, the first data that is switched according to the newly selected connection memory page are the a1 bytes of the second frame following the first j0 byte transmitted by the tse after offset rj0dly + 40 cycles. in more absolute terms, the first a1s transmitted by the tse between offset rj0dly + 40 + 19416 cycles and rj0dly + 47 + 19416 cycles, represent the first data switched according the connection memory page selected by cmp at the rj0fp pulse time 0.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 document id: pmc-1991258, issue 7 figure 22 cmp timing tp[ x ]/ tn[ x ] ... sysclk rj0fp s4,3/ a2 s1,1/j0 s2,1/ z0 ... valid cmp valid x x rj0dly + delay (40 to 47 cycles) to j0 s1,1/ a1 s2,1/ a1 ... ... ... ... s3,1/ a1 delay to second frame a1: 19416 cycles figure 23 below shows the delay from the psel bits, spsel, ipsel, and epsel, to their effect datastream at the transmit serial data links. the psel bits are written asynchronously with respect to the system clock, so use of the psel bits to effect switching connection memory pages should be avoided if switching on a particular frame is required. additionally the user can avoid changing psel bits close to the point in time when psel bits are sampled by the synchronous logic. if the frame pulse occurs at time 0, ipsel is sampled at time rj0dly, spsel is sampled at time rj0dly+15, and epsel is sampled at time rj0dly+17. switchover is delayed internally for approximately a frame. page switc hover occurs on frame boundaries, with the a1 bytes switching on the new settings. the frame switched by the newly selected connection memory page first appears on the transmit serial data links between offset rj0dly+40+9699 cycles and rj0dly+47+9696 cycles. figure 23 psel timing tp[ x ]/ tn[ x ] ... sysclk rj0fp s4,3/ a2 s1,1/j0 s2,1/ z0 ... psel rj0dly+ delay(40-47 cycles) to j0 s1,1/ a1 s2,1/ a1 ... ... ... ... s3,1/ a1 delay to next frame a1: 9696 cycles
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 document id: pmc-1991258, issue 7 14 absolute maximum ratings maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. note: if a voltage is applied to an input pin when the device is powered down, the current needs to be limited below 20ma and the maximum voltage rating does not apply. table 18 absolute maximum ratings storage temperature -40c to +125c 1.8v supply voltage (vddi, avdl, csu_avdl) -0.3v to +2.5v 3.3v supply voltage (vddo, avdh, csu_avdh) -0.3v to +4.6v input pad tolerance -2v < vddo < +2v for 10ns, 100ma max output pad overshoot limits -2v < vddo < +2v for 10ns, 20ma max voltage on any digital pin -0.5v to vddo+0.5v voltage on lvds pin -0.5v to avdh + 0.5v static discharge voltage 1000 v latch-up current on rn[i], rp[i], tn[i], tp[i] pins 90 ma latch-up current on resk pin 50 ma latch-up current 100 ma except rn[i], rp[i], tn[i], tp[i], and resk dc input current 20 ma lead temperature +300c absolute maximum junction temperature +150c
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 document id: pmc-1991258, issue 7 15 power information 15.1 power requirements table 19 power requirements conditions parameter typ 1,3 high4 max2 units iddop vddi (1.8v) 2300 - 2540 ma iddop avdl (1.8 v) 775 - 962 ma iddop vddo (3.3 v) 1.4 - 2.4 ma iddop avdh (3.3 v) 837 - 889 ma iddop csu_avdh (3.3 v) 42 - 48 ma all serial links enabled total power 8.4 9.2 - w notes: 1. typical idd values are calculated as the mean value of current under the following conditions: typically processed silicon, nominal supply voltage, tj=60 c, outputs loaded with 30 pf (if not otherwise specified), and a normal amount of traffic or signal activity. these values are suitable for evaluating typical device performance in a system. 2. max idd values are currents guaranteed by the produ ction test program and/or characterization over process for operating currents at the maximum operating voltage and operating temperature that yields the highest current. outputs are assumed to be loaded with 30pf (if not otherwise specified). 3. typical power values are calculated using the formula: power = i(vddnomi x iddtypi) where i denotes all the various power supplies on the device, vddnomi is the nominal voltage for supply i, and iddtypi is the typical current for supply i (as defined in note 1 above). these values are suitable for evaluating typical device performance in a system. 4. high power values are a ?normal high power? estimate, calculated using the formula: power = i(vddmaxi x iddhighi) where i denotes all the various power supplies on the device, vddmaxi is the maximum operating voltage for supply i, and iddhighi is the current for supply i. iddhigh values are calculated as the mean value plus two sigmas (2 ) of measured current under the following conditions: tj=105 c, outputs loaded with 30 pf (if not otherwise specified). these values are suitable for evaluating board and device thermal characteristics.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 document id: pmc-1991258, issue 7 15.2 power sequencing due to esd protection structures in the pads it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme conditions, incorrect power sequencing may damage these esd protection devices or trigger latch up. the recommended power supply sequencing is as follows: 1. the 1.8 v supplies can come up at the same time or after the 3.3 v supplies as long as the 1.8v supplies never exceed the 3.3v supplies by more than 0.3v. 2. analog supplies must not exceed digital supplies of the same nominal voltage by more than 0.3v. 3. data applied to i/o pins must not exceed vddo by more than 0.3v unless the data is current-limited to 20 ma *. there are no power-up ramp rate restrictions. the tse must be powered down according to the same restrictions above. * these rules are intended to allow for hot-swap of lvds signals, as the differential links are appropriately current-limited. 15.3 power supply filtering the following power supply filtering is recommended to achieve maximum power supply noise tolerance. see figure 24 for an example rc filter. csu_avdh: 3.3 ohm, 100nf, 10nf csu_avdl: 0.47 ohm, 4.7 uf, 10nf other avdh: 3.3 ohm, 1.0uf, 10nf other avdl: 0 ohm, 100nf, 10n f
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 document id: pmc-1991258, issue 7 figure 24 sample rc filter r +3.3/ 1.8 v c1 c2 analog pin
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 document id: pmc-1991258, issue 7 16 d.c. characteristics t a =-40c to t j= +125c, v vddi = v vdditypical 5%, v vddo = v ddotypical 5% (typical conditions: t j = 25c, v vddi = 1.8v, v vddo = 3.3v) table 20 d.c. characteristics symbol parameter min typ max units conditions v vddi power supply at 1.8v 1.71 1.8 1.89 volts v avdl power supply at 1.8v 1.71 1.8 1.89 volts v vddo power supply at 3.3v 3.135 3.3 3.465 volts v avdh power supply at 3.3v 3.135 3.3 3.465 volts v csu_avdh power supply at 3.3v 3.135 3.3 3.465 volts v il input low voltage 0 0.8 volts guaranteed input low voltage. v ih input high voltage 2.0 volts guaranteed input high voltage. v ol output or bi-directional low voltage .1v 0.4 volts guaranteed output low voltage at vdd=2.97v and i ol =maximum rated for pad. v oh output or bi-directional high voltage 2.4 2.8 volts guaranteed output high voltage at vdd=2.97v and i oh =maximum rated current for pad. v t+ reset input high voltage 2.2 volts applies to sysclk, rstb and trstb only. v t- reset input low voltage 0.8 volts applies to sysclk, rstb and trstb only. i ilpu input low current -200 -50 -4 a v il = gnd. notes 1 and 3. i ihpu input high current -10 0 +10 a v ih = v dd . notes 1 and 3. i il input low current -10 0 +10 a v il = gnd. notes 2 and 3. i ih input high current -10 0 +10 a v ih = v dd . notes 2 and 3.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 document id: pmc-1991258, issue 7 c in input capacitance 5 pf t a =25c, f = 1 mhz c out output capacitance 5 pf t a =25c, f = 1 mhz c io bi-directional capacitance 5 pf t a =25c, f = 1 mhz v icm lvds input common-mode range 0 2.4 v |v idm | lvds input differential sensitivity 100 mv r in lvds differential input impedance 85 100 115 v loh lvds output voltage high 1375 1475 mv r load =100 1% v lol lvds output voltage low 925 1025 mv r load =100 1% v odm lvds output differential voltage 300 350 400 mv r load =100 1% v ocm lvds output common-mode voltage 1125 1200 1275 mv r load =100 1% r o lvds output impedance, differential 85 110 115 | v odm | change in |v odm | between ?0? and ?1? 25 mv r load =100 1% v ocm change in v ocm between ?0? and ?1? 25 mv r load =100 1% i sp , i sn lvds short- circuit output current 10 ma drivers shorted to ground i spn lvds short- circuit output current 10 ma drivers shorted together notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor. 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing.)
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 document id: pmc-1991258, issue 7 17 microprocessor interface timing characteristics ta=-40c to tj=+125c, v vddi = v vdditypical 5%, v vddo = v ddotypical 5% (typical conditions: t j = 25c, v vddi = 1.8v, v vddo = 3.3v) table 21 microprocessor interface read access symbol parameter min max units tsar address to valid read set-up time 10 ns thar address to valid read hold time 5 ns tsalr address to latch set-up time 10 ns thalr address to latch hold time 10 ns tvl valid latch pulse width 5 ns tslr latch to read set-up 0 ns thlr latch to read hold 5 ns tprd valid read to valid data propagation delay 70 ns tzrd valid read negated to output tri-state 20 ns tzinth valid read negated to intb high (wcimode=0) 50 ns
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 document id: pmc-1991258, issue 7 figure 25 microprocessor interface read timing vali d tzrd tprd tzinth thlr tslr thalr tvl tsalr tvl thar tsar a[8:0] ale (csb+rdb) intb d[7:0] notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[15:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alr , th alr , tv l , ts lr , and th lr are not applicable. 5. parameter th ar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 document id: pmc-1991258, issue 7 table 22 microprocessor interface write access symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns tz inth valid write negated to intb high (wcimode = 1) 50 ns figure 26 microprocessor interface write timing valid thlw thdw tsdw tvwr tvwr tslw thalw tvl tsalw tvl thaw tsaw a[8:0] ale (csb+wrb) d[15:0] tzinth intb
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 document id: pmc-1991258, issue 7 notes on microprocessor interface write timing: 1 a valid write cycle is defined as a logical or of the csb and the wrb signals. 2 in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alw , th alw , tv l , ts lw , and th lw are not applicable. 3 parameter th aw is not applicable if address latching is used. 4 when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5 when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 document id: pmc-1991258, issue 7 18 a.c. timing characteristics ta=-40c to tj=+125c, v vddi = v vdditypical 5%, v vddo = v ddotypical 5% (typical conditions: t j = 25c, v vddi = 1.8v, v vddo = 3.3v) 18.1 input timing table 23 tse input timing (figure 27) symbol description min max units fsysclk sysclk frequency (nominally 77.76 mhz ) 77.76-100ppm 77.76+100ppm mhz thisysclk sysclk high pulse width 5 ns tlosysclk sysclk low pulse width 5 ns tscmp cmp set-up time 3 ns thcmp cmp hold time 0 ns tsrj0 rj0fp set-up time 3 ns thrj0 rj0fp hold time 0 ns figure 27 tse input timing sysclk rj0fp ts rj0 th rj0 cmp ts cmp th cmp tlo sysclk tlo sysclk notes on input timing: when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 document id: pmc-1991258, issue 7 when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 18.2 output timing table 24 tse output timing (figure 28) symbol description min max units tp tj0 sysclk high to tj0fp valid 1 22 ns figure 28 tse output timing sysclk tj0fp tp tj0 notes on output timing: output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. output propagation delays are measured with a 30 pf load on the outputs except where indicated.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 document id: pmc-1991258, issue 7 18.3 reset timing table 25 rstb timing (figure 29) symbol parameter min max units tv rstb rstb pulse width 100 ns figure 29 rstb timing rstb tv rstb
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 document id: pmc-1991258, issue 7 18.4 serial tel ecombus interface table 26 serial telecombus interface symbol description min typical max units frlvds rp[64:1], rn[64:1] bit rate 10f sysclk - 100ppm 10f sysclk 10f sysclk - 100ppm mbps tfall vodm fall time, 80%-20%, (rload=100 1%) 200 300 400 ps trise vodm rise time, 20%-80%, (rload=100 1%) 200 300 400 ps tskew differential skew 50 ps the min and max f rlvds specification is to accommodate transients between generated clocks. the mean data rate must be exactly 10f sysclk . fifo overrun/underrun in the r8fa and t8de will result if the mean data rate differs from 10f sysclk . a common system clock needs to be used for all devices with serial telecombus interfaces. 18.5 jtag port interface table 27 jtag port interface (figure 30) symbol description min max units ftck tck frequency 4 mhz thitck tck hi pulse width 100 ns tlotck tck lo pulse width 100 ns tstms tms set-up time to tck 25 ns thtms tms hold time to tck 25 ns tstdi tdi set-up time to tck 25 ns thtdi tdi hold time to tck 25 ns tptdo tck low to tdo valid 2 35 ns tvtrstb trstb pulse width 100 ns
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 document id: pmc-1991258, issue 7 figure 30 jtag port interface timing tlotck tlotck thitck thitck tvtrstb tvtrstb tptdo thtms tstms thtdi tstdi tck tdi tms tdo trstb
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 document id: pmc-1991258, issue 7 19 ordering information part no. description pm5372-bi 560 ultra ball grid array (ubga)
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 document id: pmc-1991258, issue 7 20 thermal information this product is designed to operate over a wide temperature range when used with a heat sink and is suited for outside plant equipment 1 . table 28 outside plant thermal information maximum long-term operating junction temperature (t j ) to ensure adequate long- term life. 105 c maximum junction temperature (t j ) for short-term excursions with guaranteed continued functional performance 2 . this condition will typically be reached when the local ambient temperature reaches 85 c. 125 c minimum ambient temperature (t a ) -40 c table 29 device compact model 3 jc 0.1 c/w jb 4.0 c/w table 30 heat sink requirements sa + cs 4 [(105-70)/p]- jc c/w 5 sa and cs are required for long-term operation jb jc board device compact model cs sa junction case heat sink ambient operating power is dissipated in the package at the worst-case power supply. power depends upon the operating mode. please refer to ?high? power values in section 15.1power requirements. notes 1. the minimum ambient temperature requirement for outside plant equipment meets the minimum ambient temperature requirement for industrial equipment 2. short-term is used as defined in telcordia te chnologies generic requirements gr-63-core core. 3. junction-to-case thermal resistance, is a measured nominal value plus two sigma. jb , the junction-to- board thermal resistance, is obtained by simulating conditions described in jedec standard jesd 51- 8.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 document id: pmc-1991258, issue 7 4. sa is the thermal resistance of the heat sink to ambient. cs is the thermal resistance of the heat sink attached material. the maximum sa required for the airspeed at the location of the device in the system with all components in place. in this formula p is the operating power.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:31:42 pm tse transmission switch element datasheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 document id: pmc-1991258, issue 7 21 mechanical information a 2 a a 1 side view seating plane c bbb c ddd c a1 ball corner a1 ball id ink mark d a e b aaa a (4x) notes: 1) all dimensions in millimeter. 4) dimension ddd denotes coplanarity. 3) dimension bbb denotes parallel. 2) dimension aaa denotes package body profile. package type : 560 thermally enhanced ball grid array - ubga dim. a a 1 a 2 dd 1 ee 1 bd aaabbb min. 0.40 0.92 39.90 39.90 0.50 nom. 0.50 0.97 40.00 38.00 40.00 38.00 0.63 max. 0.60 1.02 40.10 40.10 0.70 0.20 0.25 e - - 1.00 1.32 1.47 1.62 ddd - - - - ccc 0.20 - - m,n 39x39 body size : 40 x 40 x 1.47 mm - - - - - - - - - 0.20 - top view b m 0.30 0.10 c cab m 20 18 16 14 12 10 8 6 4 2 22 24 26 28 32 34 36 38 30 19 17 15 13 11 9 753 21 23 25 27 29 31 33 35 37 39 1 bottom view extent of encapsulation e e a c e g j l n r u w aa ac ae aj al ag an ar au aw b d f h k m p t v y ab ad af ak ah am ap at av e1, n d1, m a1 ball corner

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